CY7C1357C-133AXI Cypress Semiconductor Corp, CY7C1357C-133AXI Datasheet - Page 8
![IC SRAM 9MBIT 133MHZ 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C1357C-133AXI
Manufacturer Part Number
CY7C1357C-133AXI
Description
IC SRAM 9MBIT 133MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet
1.CY7C1357C-133AXI.pdf
(28 pages)
Specifications of CY7C1357C-133AXI
Memory Size
9M (512K x 18)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
133MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
6.5 ns
Maximum Clock Frequency
133 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3.135 V
Maximum Operating Current
250 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
2
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1357C-133AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1357C-133AXIT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Document #: 38-05539 Rev. *E
Pin Definitions
Functional Overview
The CY7C1355C/CY7C1357C is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states
during Write-Read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN). If CEN is HIGH, the clock signal is not recog-
nized and all internal states are maintained. All synchronous
operations are qualified with CEN. Maximum access delay
from the clock rise (t
Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed Write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 7.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
TMS
TCK
NC
V
SS
1
/DNU
, CE
Name
3
2
are ALL asserted active, (3) the Write Enable input
, CE
3
) active at the rising edge of the clock. If Clock
JTAG serial input
CDV
(continued)
Synchronous
Ground/DNU
) is 6.5 ns (133-MHz device).
JTAG
Clock
I/O
–
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
No Connects. Not internally connected to the die. 18 Mbit, 36 Mbit, 72 Mbit, 144 Mbit, 288
Mbit, 576 Mbit and 1G are address expansion pins and are not internally connected to the
die.
This pin can be connected to Ground or should be left floating.
1
, CE
X
can be used to
2
, CE
3
) and an
1
SS
, CE
. This pin is not available on TQFP packages.
2
,
Burst Read Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
is asserted LOW. The address presented to the address bus
is loaded into the address register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQP
On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
write capability that is described in the Truth Table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1355C/CY7C1357C is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQs and DQP
Doing so will tri-state the output drivers. As a safety
X
signals. The CY7C1355C/CY7C1357C provides byte
3
are ALL asserted active, and (3) the Write signal WE
Description
X
.
DD
CY7C1355C
CY7C1357C
. This pin is not
Page 8 of 28
X
1
inputs.
, CE
2
X
,
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