CY7C1514V18-167BZC Cypress Semiconductor Corp, CY7C1514V18-167BZC Datasheet
CY7C1514V18-167BZC
Specifications of CY7C1514V18-167BZC
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CY7C1514V18-167BZC Summary of contents
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... DDR interfaces. Each address location is associated with two 18 bit words (CY7C1512V18 bit words (CY7C1514V18) that burst sequentially into or out of the device. Because data can be trans- ferred into and out of the device on every rising edge of both input ...
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... Logic Block Diagram (CY7C1512V18 [17:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1514V18 [35:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document #: 38-05489 Rev. *G Write Write Address Reg ...
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... Pin Configuration The pin configuration for CY7C1512V18, and CY7C1514V18 follow. Figure 1. 165-Ball FBGA ( 1.4 mm) Pinout /144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 P NC ...
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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each 18) for CY7C1512V18, and arrays each 36) for CY7C1514V18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1512V18 and 20 address inputs for CY7C1514V18. These inputs are ignored when the appropriate port is deselected ...
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... Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF Reference measurement points. V Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document #: 38-05489 Rev. *G CY7C1512V18 CY7C1514V18 Pin Description Page [+] Feedback ...
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... Functional Overview The CY7C1512V18, and CY7C1514V18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required ...
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... The DLL may be on page disabled by applying ground to the DOFF pin. For information refer to the application note QDRII/DDRII/QDRII+/DDRII+. Figure 2. Application Example SRAM # 250ohms CQ/CQ Vddq/2 CY7C1512V18 CY7C1514V18 AN5062, DLL Considerations in SRAM # 250ohms CQ/CQ Page [+] Feedback ...
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... Truth Table The truth table for CY7C1512V18, and CY7C1514V18 follow. Operation Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. ...
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... Write Cycle Descriptions The write cycle description table for CY7C1514V18 follow. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Document #: 38-05489 Rev Comments – During the data portion of a write sequence, all four bytes (D the device. L– ...
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... TAP controller must be moved into the Update-IR state. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the CY7C1512V18 CY7C1514V18 “TAP Controller Block Diagram” when SS on page 16 shows the order in which “ ...
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... Document #: 38-05489 Rev. *G CY7C1512V18 CY7C1514V18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board ...
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... IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05489 Rev. *G [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1512V18 CY7C1514V18 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... Boundary Scan Register TAP Controller Test Conditions = −2 −100 μ 2 100 μ GND ≤ V ≤ − /2), Undershoot: V (AC) > 1.5V (Pulse width less than t CYC IL CY7C1512V18 CY7C1514V18 Selection TDO Circuitry Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD μA – ...
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... Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 38-05489 Rev. *G Description [14] Figure 3. TAP Timing and Test Conditions 0.9V 1.8V 50Ω TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1512V18 CY7C1514V18 Min Max Unit 50 20 MHz ALL INPUT PULSES 0.9V t TCYC t TDOX Page ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05489 Rev. *G Value CY7C1512V18 CY7C1514V18 000 000 11010011010100100 00000110100 00000110100 1 Description CY7C1512V18 CY7C1514V18 Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. 1 Indicates the presence register. Bit Size 109 ...
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... Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1512V18 CY7C1514V18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...
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... DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency. . REF Figure 4. Power Up Waveforms > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tie to V DDQ ) CY7C1512V18 CY7C1514V18 . KC Var Start Normal Operation Page [+] Feedback ...
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... During this time V < V and /2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1512V18 CY7C1514V18 Test Description Typ Max* Unit Conditions Logical 25°C 320 368 Single Bit Upsets Logical Multi 25° ...
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... DD Both Ports Deselected, (x36) ≥ V ≤ 1/t , 200MHz (x18) MAX CYC Inputs Static (x36) 167MHz (x18) (x36) Test Conditions CY7C1512V18 CY7C1514V18 Min Typ Max Unit 400 mA 450 380 400 360 370 Min Typ Max Unit V + 0.2 – – V REF – – ...
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... V 0.75V R = 50Ω REF OUTPUT DEVICE 0.25V 5 pF UNDER ZQ TEST RQ = 250Ω INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1512V18 CY7C1514V18 Max Unit = 1.5V 5.5 pF DDQ 8 165 FBGA Unit Package 16.3 °C/W 2.1 °C/W [20] ALL INPUT PULSES 1.25V 0.75V SLEW RATE ...
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... V is 0.5 ns for 200 MHz, and 250 MHz frequencies. AC Test Loads and Waveforms and t less than t . CLZ CHZ CO CY7C1512V18 CY7C1514V18 250 MHz 200 MHz 167 MHz Min Max Min Max Min Max 4.0 8.4 5 ...
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... In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document #: 38-05489 Rev. *G WRITE READ WRITE NOP CYC t KHKH D31 D50 D51 D60 Q00 Q01 Q20 t CQDOH t DOH CYC t CCQO t CQOH t CCQO CY7C1512V18 CY7C1514V18 [26, 27, 28] WRITE NOP D61 Q21 Q40 Q41 t CHZ t CQD DON’T CARE UNDEFINED Page [+] Feedback ...
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... CY7C1512V18-250BZXI 200 CY7C1512V18-200BZC CY7C1514V18-200BZC CY7C1512V18-200BZXC CY7C1514V18-200BZXC CY7C1512V18-200BZI CY7C1512V18-200BZXI CY7C1514V18-200BZXI 167 CY7C1512V18-167BZC CY7C1514V18-167BZC CY7C1512V18-167BZXC CY7C1514V18-167BZXC CY7C1514V18-167BZI CY7C1512V18-167BZXI Document #: 38-05489 Rev. *G www.cypress.com Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
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... Package Diagram Document #: 38-05489 Rev. *G Figure 7. 165-Ball FBGA ( 1.4 mm) CY7C1512V18 CY7C1514V18 51-85195 *B Page [+] Feedback ...
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... Document History Page Document Title: CY7C1512V18/CY7C1514V18, 72 Mbit QDR Document Number: 38-05489 Orig. Of Submission Revision ECN Change Date ** 201260 NJY See ECN *A 257089 NJY See ECN *B 319496 SYT See ECN *C 403231 NXR See ECN *D 467290 NXR See ECN Document #: 38-05489 Rev. *G ® ...
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... Document History Page Document Title: CY7C1512V18/CY7C1514V18, 72 Mbit QDR Document Number: 38-05489 *E 2511080 VKN/AESA See ECN *F 2549270 PYRS 08/06/08 *G 2756998 VKN 08/28/09 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...