SST25VF010A-33-4C-SAE Microchip Technology, SST25VF010A-33-4C-SAE Datasheet - Page 15

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SST25VF010A-33-4C-SAE

Manufacturer Part Number
SST25VF010A-33-4C-SAE
Description
IC FLASH SER 1MB 33MHZ SPI 8SOIC
Manufacturer
Microchip Technology

Specifications of SST25VF010A-33-4C-SAE

Memory Type
FLASH
Memory Size
1M (128K x 8)
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (3.9mm Width)
Format - Memory
FLASH
Speed
33MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Architecture
Sectored
Interface Type
SPI
Access Time
33 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
10 mA
Mounting Style
SMD/SMT
Organization
4 KB x 32
Clock Frequency
33MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SOIC
No. Of Pins
8
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SST25VF010A-33-4C-SAE
Manufacturer:
SST
Quantity:
20 000
Part Number:
SST25VF010A-33-4C-SAE-T
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
1 Mbit SPI Serial Flash
SST25VF010A
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-Write-
Status-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write-
©2006 Silicon Storage Technology, Inc.
FIGURE 12: W
FIGURE 13: W
RITE
RITE
E
D
NABLE
ISABLE
(WREN) S
(WRDI) S
SCK
CE#
SCK
CE#
SO
SO
SI
SI
EQUENCE
EQUENCE
MODE 3
MODE 0
MODE 3
MODE 0
HIGH IMPEDANCE
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
MSB
0 1 2 3 4 5 6 7
15
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
04
06
1265 F13.0
1265 F12.0
S71265-02-000
Data Sheet
1/06

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