SST49LF016C-33-4C-WHE Microchip Technology, SST49LF016C-33-4C-WHE Datasheet - Page 18
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SST49LF016C-33-4C-WHE
Manufacturer Part Number
SST49LF016C-33-4C-WHE
Description
IC FLASH SER LPC 16MBIT 32TSOP
Manufacturer
Microchip Technology
Datasheets
1.SST49LF080A-33-4C-NHE.pdf
(2 pages)
2.SST49LF080A-33-4C-NHE.pdf
(2 pages)
3.SST49LF016C-33-4C-NHE.pdf
(36 pages)
Specifications of SST49LF016C-33-4C-WHE
Memory Type
FLASH
Memory Size
16M (2M x 8)
Operating Temperature
0°C ~ 85°C
Package / Case
32-TSOP
Format - Memory
FLASH
Speed
33MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Data Bus Width
8 bit
Architecture
Sectored
Interface Type
Parallel, Serial
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
18 mA
Mounting Style
SMD/SMT
Organization
4 KB x 512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SST49LF016C-33-4C-WHE
Manufacturer:
Microchip Technology
Quantity:
135
Data Sheet
REGISTERS
There are five types of registers available on the
SST49LF016C, the multi-byte Read/Write configuration
registers (for Firmware Memory cycle), General Purpose
Inputs registers, Block Locking registers, Security ID regis-
ter, and the JEDEC ID registers. These registers appear at
their respective address location in the 4 GByte system
memory map. Unused register locations will read as 00H.
Any attempt to read or write any register during an internal
Write operation will be ignored.
Read or write access to the register during an internal Pro-
gram/Erase operation will be completed as follows:
•
•
Multi-Byte Read/Write Configuration
Registers (Firmware Memory Cycle)
The multi-byte read/write configuration (MBR) registers are
four 8-bit read-only registers located at addresses
FFBC0005-FFBC0008 for boot configured device (see
Table 13). These registers are accessible using Firmware
Memory Read cycle only. These registers contain informa-
tion about multi-byte read and write access sizes that will
be accepted for Firmware Memory multi-byte Read com-
mands. The registers are not available in AAI mode.
TABLE 13: Multi-byte Read/Write Configuration Registers (Firmware Memory Cycle Only)
©2008 Silicon Storage Technology, Inc.
Register
MULTI_BYTE_READ_L
MULTI_BYTE_READ_H
MULTI_BYTE_WRITE_L
MULTI_BYTE_WRITE_H
1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory
Multi-byte Read/Write Configuration registers,
General Purpose Inputs register, and Block Lock-
ing registers can be accessed normally
Security ID register and the JEDEC ID registers
can not be accessed (reading these registers will
return unused register data 00H).
map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system.
Register Address
FFBC 0005H
FFBC 0006H
FFBC 0007H
FFBC 0008H
1
0100 1011b
0000 0000b
0000 0011b
0000 0000b
Data
18
In case of multi-byte Firmware Memory register reads, the
device will return register data for the addressed register
until the command finishes, or is aborted.
General Purpose Inputs Register
The General Purpose Inputs register (GPI_REG) passes
the state of GPI[4:0] pins on the SST49LF016C. It is rec-
ommended that the GPI[4:0] pins be in the desired state
before LFRAME# is brought low for the beginning of the
bus cycle, and remain in that state until the end of the cycle.
There is no default value since this is a pass-through regis-
ter. The GPI_REG register for the boot device appears at
FFBC0100H in the 4 GByte system memory map, and will
appear elsewhere if the device is not the boot device (see
Table 12). This register is not available to be read when the
device is in an Erase/Program operation. In case of multi-
byte Firmware Memory cycle register reads, the device will
return register data for the addressed register until the com-
mand finishes, or is aborted.
TABLE 12: General Purpose Register
Register
GPI_REG
Access Description
1. Address shown in this column is for boot device only.
Address locations should appear elsewhere in the 4
GByte system memory map depending on ID strapping
values on ID[3:0] pins when multiple LPC memory
devices are used in a system.
R
R
R
R
Device supports 1,2,4, 16, 128 Byte reads
Future Expansion for Read
Device supports 1, 2, 4 Byte Write
Future Expansion for Write
Register Address
FFBC 0100H
16 Mbit LPC Serial Flash
1
SST49LF016C
Default
Value
S71237-08-000
N/A
Access
T12.0 1237
T13.0 1237
R
5/08