HYB25D512800CE-5 Qimonda, HYB25D512800CE-5 Datasheet
HYB25D512800CE-5
Specifications of HYB25D512800CE-5
Related parts for HYB25D512800CE-5
HYB25D512800CE-5 Summary of contents
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... HYI25D512800CT-5,HYI25D512800CC-6, HYI25D512800CF-6 and HYI25D512800CC-5 Package Outline Figures updated Previous Revision: Rev. 1.31, 2006-09 Qimonda update We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics. 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and ...
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... Description The 512-Mbit is a high-speed CMOS, dynamic random- access memory containing 536, 870, 912 bits internally configured as a quad-bank DRAM. The 512-Mbit Double-Data-Rate SDRAM uses a double- data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... DDR400B ×4 HYB25D512400CE-5 DDR400B ×4 HYB25D512400CFL-5 DDR400B ×8 HYB25D512800CFL-5 DDR400B ×8 HYB25D512800CEL-5 DDR400B ×16 HYB25D512160CE-5 DDR400B ×4 HYB25D512400CF-5 DDR400B ×8 HYB25D512800CE-5 DDR400B ×8 HYB25D512800CF-5 DDR400B DDR333B( 2.5-3-3) ×16 HYB25D512160CEL-6 DDR333B ×16 HYB25D512160CF-6 DDR333B ×16 HYB25D512160CFL-6 DDR333B ×4 HYB25D512400CE-6 DDR333B ×4 HYB25D512400CFL-6 DDR333B × ...
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... HYI25D512160CC-6 ×16 HYI25D512160CT-6 ×8 HYI25D512800CC-6 ×8 HYI25D512800CT-6 1) For detailed information regarding Product Type of Qimonda please see chapter "Product Nomenclature" of this datasheet. 2) CAS: Column Address Strobe 3) RCD: Row Column Delay 4) RP: Row Precharge Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) Ordering Information for non RoHS Compliant Products ...
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Configuration This chapter contains the chip configuration and block diagrams. 2.1 Configuration for TSOPII-66 The pin configuration of a DDR SDRAM is listed by function in are explained in Table 5 and Table 6 respectively. Pin# Name Pin Type ...
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Pin# Name Pin Type Data Signals ×4 Organization 5 DQ0 I/O 11 DQ1 I/O 56 DQ2 I/O 62 DQ3 I/O Data Strobe ×4 Organization 51 DQS I/O Data Mask ×4 Organization Data Signals × 8 Organization 2 ...
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Pin# Name Pin Type Data Strobe ×16 Organization 51 UDQS I/O 16 LDQS I/O Data Mask ×16 Organization 47 UDM I 20 LDM I Power Supplies REF 3, 9, 15, 55 PWR DDQ 1, 18, ...
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Abbreviation Description I Standard input-only pin. Digital levels O Output. Digital levels I/O I bidirectional input/output signal AI Input. Analog levels PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminalted Logic (SSTL2) LV-CMOS Low ...
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Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Pin Configuration TSOPII-66 11 Date: 2007-12-13 Internet Data Sheet FIGURE 1 ...
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Configuration for TFBGA-60 The ball configuration of a DDR SDRAM is listed by function in are explained in Table 8 and Table 9 respectively. Ball# Name Pin Type Clock Signals G2 CK1 I G3 CK1 I H3 CKE I ...
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Ball# Name Pin Type Data Mask ×4 Organization Data Signals × 8 Organization A8 DQ0 I/O B7 DQ1 I/O C7 DQ2 I/O D7 DQ3 I/O D3 DQ4 I/O C3 DQ5 I/O B3 DQ6 I/O A2 DQ7 I/O ...
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Ball# Name Pin Type A9, B2, C8, D2, V PWR DDQ E8 A7, F8 PWR DD A1, B8, C2, D8, V PWR SSQ E2 A3, F2 PWR SS Not Connected ×4 Organization A2, A8, B1, B9, ...
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Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Configuration for x4 Organization, TFBGA-60, Top View 15 Date: 2007-12-13 Internet Data Sheet FIGURE 2 ...
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Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Configuration for x8 Organization, TFBGA-60, Top View 16 Date: 2007-12-13 Internet Data Sheet FIGURE 3 ...
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Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Configuration for x16 Organization, TFBGA-60, Top View 17 Date: 2007-12-13 Internet Data Sheet FIGURE 4 ...
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Functional Description The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. 3.1 Mode Register Definition The Mode Register is used to define the specific mode of operation of the DDR SDRAM. 1) Field Bits Type Description ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined ...
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Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register. 1) Field Bits Type Description DLL 0 w DLL Status Drive Strength MODE ...
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Truth Tables The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate SDRAM. Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, ...
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Current State CKE n-1 CKEn Previous Current Cycle Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks Idle H L Bank(s) Active ...
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Current State CS RAS CAS WE Command Any Idle Row Active ...
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Truth Table 5: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Command Any Idle Row ...
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READ data and WRITE data must be avoided). The minimum delay from a read or write command with auto precharge enable command to a different banks is summarized in ...
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Electrical Characteristics This chapter describes the electrical characteristics. 5.1 Operating Conditions This chapter contains the operating conditions tables. Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply ...
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Parameter Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS These values are guaranteed by design and ...
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Parameter Symbol V Device Supply Voltage DD V Output Supply Voltage DDQ V V Supply Voltage SSQ I/O Supply Voltage V Input Reference Voltage REF V I/O Termination Voltage TT (System) V Input High (Logic1) Voltage IH.DC V ...
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AC Characteristics Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I Specifications and Conditions, and Electrical Characteristics and AC Timing. DD Notes V 1. All voltages referenced ...
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Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs ...
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Parameter Symbol t DQS falling edge hold time from DSH CK (write cycle) t DQS falling edge to CK setup DSS time (write cycle) t Clock Half Period HP t Data-out high-impedance time HZ from CK/CK t Address and control ...
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Parameter Symbol t Write preamble setup time WPRES t Write postamble WPST t Write recovery time WR t Internal write to read command WTR delay t Exit self-refresh to non-read XSNR command t Exit self-refresh to read XSRD command T ...
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Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page ...
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DDR333 Symbol Typ. Max DD0 DD1 1.1 4.6 DD2P DD2F DD2Q DD3P DD3N ...
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Package Outlines The package used for this product family. Notes 1. Drawing according to ISO 8015 2. Dimensions General tolerances +/- 0.15 Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Package Outline P(G)-TSOPII-66 35 Date: 2007-12-13 ...
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Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Package Outline P-TFBGA-60 36 Date: 2007-12-13 Internet Data Sheet FIGURE 7 ...
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Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Package Outline PG-TFBGA-60 37 Date: 2007-12-13 Internet Data Sheet FIGURE 8 ...
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... Product Nomenclature For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. Example for Field Number 1 2 DDR SDRAM HYB 25 Field Description 1 Qimonda Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component Density [Mbit] 5 Number of I/Os 6 Product Variations 7 Die Revision 8 Package, Lead-Free Status ...
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List of Illustrations Figure 1 Pin Configuration TSOPII- ...
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... Electrical Characteristics and DC Operating Conditions Table 22 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 23 AC Timing - Absolute Specifications Table 24 I Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DD Table 25 I Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DD Table 26 Example for Nomenclature Fields Table 27 DDR Memory Components Rev. 1.41, 2007-12 03292006-3TFJ-HNV3 HY[B/I]25D512[40/80/16]0C[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM 40 Date: 2007-12-13 Internet Data Sheet ...
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Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...