MT47H32M8BP-3:B TR Micron Technology Inc, MT47H32M8BP-3:B TR Datasheet - Page 107

IC DDR2 SDRAM 256MB 60-FBGA

MT47H32M8BP-3:B TR

Manufacturer Part Number
MT47H32M8BP-3:B TR
Description
IC DDR2 SDRAM 256MB 60-FBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H32M8BP-3:B TR

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
256M (32M x 8)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1050-2
Figure 64: WRITE – DM Operation
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
DQS, DQS#
Bank select
Command
Address
CK#
CKE
A10
DQ 7
DM
CK
NOP 1
T0
Notes:
Bank x
ACT
RA
RA
T1
t CK
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5.
6. Subsequent rising DQS signals must align to the clock within
7. DI n = data-in for column n; subsequent elements are applied in the programmed order.
8.
9.
NOP 1
T2
these times.
t
t
t
t CH
WR starts at the end of the data burst regardless of the data mask condition.
DSH is applicable during
DSS is applicable during
t RCD
t CL
Bank x
WRITE 2
Col n
3
T3
AL = 1
NOP 1
T4
WL ± t DQSS (NOM)
WL = 2
NOP 1
t
T5
107
t
DQSS (MAX) and is referenced from CK T7 or T8.
DQSS (MIN) and is referenced from CK T6 or T7.
t WPRE
NOP 1
T6
DI
n
t RAS
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T6n
t DQSL t DQSH t WPST
256Mb: x4, x8, x16 DDR2 SDRAM
NOP 1
6
T7
T7n
NOP 1
T8
Transitioning Data
NOP 1
T9
©2003 Micron Technology, Inc. All rights reserved.
t
DQSS.
t WR 5
T10
NOP 1
One bank
All banks
Don’t Care
Bank x 4
T11
PRE
WRITE
t RPA

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