93LC56C-I/SN Microchip Technology, 93LC56C-I/SN Datasheet - Page 7

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93LC56C-I/SN

Manufacturer Part Number
93LC56C-I/SN
Description
IC EEPROM 2KBIT 3MHZ 8SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of 93LC56C-I/SN

Memory Size
2K (256 x 8 or 128 x 16)
Package / Case
8-SOIC (3.9mm Width)
Operating Temperature
-40°C ~ 85°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
2MHz, 3MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Organization
128 K x 16 or 256 x 8
Interface Type
2-Wire
Maximum Clock Frequency
2 MHz
Access Time
6 ms
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
0.5 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
93LC56C-I/SNG
93LC56C-I/SNG
93LC56C-I/SNR
93LC56C-I/SNR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
93LC56C-I/SN
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
93LC56C-I/SN
Manufacturer:
Microchi11
Quantity:
88
2.5
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3:
FIGURE 2-4:
 2003 Microchip Technology Inc.
CLK
CLK
DO
DO
CS
DI
CS
DI
V
CC
ERASE ALL (ERAL)
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
HIGH-Z
HIGH-Z
must be
1
4.5V for proper operation of ERAL.
1
ERAL TIMING FOR 93AA AND 93LC DEVICES
ERAL TIMING FOR 93C DEVICES
0
0
0
0
1
1
0
0
X
X
•••
•••
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
V
X
X
CC
Note:
must be
T
T
CSL
CSL
CSL
).
Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
T
EC
T
T
T
4.5V for proper operation of ERAL.
EC
SV
SV
CHECK STATUS
CHECK STATUS
BUSY
BUSY
READY
READY
DS21794B-page 7
HIGH-Z
HIGH-Z
T
T
CZ
CZ

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