MR2A08AYS35 EverSpin Technologies Inc, MR2A08AYS35 Datasheet - Page 9

• Manufacturer Part Number: MR2A08AYS35
• Description: IC MRAM 4MBIT 35NS 44TSOP
• Manufacturer: EverSpin Technologies Inc

Specifications of MR2A08AYS35

• Format - Memory: RAM
• Memory Type: MRAM (Magnetoresistive RAM)
• Memory Size: 4M (512K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 819-1004

Everspin Technologies © 2009
Timing Specifications
1
2
3
All write cycle timings are referenced from the last valid address to the first transition address.
Parameter
Write cycle time
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Write pulse width (G high)
Write pulse width (G low)
Data valid to end of write
Data hold time
Write low to data Hi-Z
Write high to output active
Write recovery time
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given
voltage or temperature, t
2
3
WLQZ
3
(max) < t
Figure 3.4 Write Cycle Timing 1 (W Controlled)
Table 3.4 Write Cycle Timing 1 (W Controlled)
WHQX
(min)
9
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
AVWL
AVWH
AVWH
WLWH
WLEH
WLWH
WLEH
DVWH
WHDX
WLQZ
WHQX
WHAX
Document Number: MR2A08A Rev. 4, 7/2009
Min
35
0
18
20
15
15
10
0
0
3
12
1
Max
-
-
-
-
-
-
-
-
12
-
-
MR2A08A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns