CAT25128VI-G ON Semiconductor, CAT25128VI-G Datasheet
CAT25128VI-G
Specifications of CAT25128VI-G
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CAT25128VI-G Summary of contents
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CAT25128 128-Kb SPI Serial CMOS EEPROM Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled ...
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Table 1. ABSOLUTE MAXIMUM RATINGS Operating Temperature Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions ...
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Table 5. A.C. CHARACTERISTICS Symbol Parameter f Clock Frequency SCK t Data Setup Time SU t Data Hold Time H t SCK High Time WH t SCK Low Time WL t HOLD to Output Low (Note 5) ...
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... Figure 2. Synchronous Data Timing http://onsemi.com 4 Opcode Operation 0000 0110 Enable Write Operations 0000 0100 Disable Write Operations 0000 0101 Read Status Register 0000 0001 Write Status Register 0000 0011 Read Data from Memory 0000 0010 Write Data to Memory CNS DIS HI−Z ...
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... Low X High X High allowed to protect a quarter, one half or the entire memory, by setting these bits according to Table 9. The protected blocks then become read−only. The WPEN (Write Protect Enable) bit acts as an enable for the WP pin. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1 ...
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... The CAT25128 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of the memory location( written must be outside the protected area, as defined by BP0 and BP1 bits from the status register ...
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Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16−bit address and data as shown in Figure 5. Only 14 significant address bits are used by the CAT25128. ...
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Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3 and 7 can be written using the WRSR command SCK OPCODE ...
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... Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAT25128 will respond by shifting out data on the SO pin (as shown in Figure 9). Sequentially stored data can be read out by simply continuing to run the clock ...
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... The CS input must be set high after the proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write cycle is ignored and programming is continued. Any invalid op−code will be ignored and the serial output pin (SO) will remain in the high impedance state ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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PIN#1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...
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... The standard lead finish is NiPdAu. 11. The device used in the above example is a CAT25128VI−GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 12. The SOIC, EIAJ (X) package is only available in 2,000 pcs/reel and Matte−Tin lead finish, i.e., CAT25128XI−T2. Please contact factory for availability ...