SST89E554RC-40-C-PI Microchip Technology, SST89E554RC-40-C-PI Datasheet - Page 42

• Manufacturer Part Number: SST89E554RC-40-C-PI
• Description: 8-bit Microcontrollers - MCU 32KB+8KB 40ns
• Manufacturer: Microchip Technology

Specifications of SST89E554RC-40-C-PI

• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: PDIP-40
• Mounting Style: Through Hole
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• On-chip Dac: No
• Processor Series: FlashFlex
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

EOL Data Sheet
TABLE
Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.
TABLE
Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.
©2007 Silicon Storage Technology, Inc.
Operation
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Prog-SB1
Prog-SB2
Prog-SB3
Prog-SC0
Enable-Clock-Double
Operation
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Prog-SB1
Prog-SB2
Prog-SB3
Prog-SC0
Prog-SC1
Enable-Clock-Double
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. X can be V
5. Refer to Table 4-5 for address resolution
6. AH = Address high order byte
7. AL = Address low order byte
8. DI = Data Input, DO = Data Output, all other values are in hex.
9. Instruction must be located in Block 1 or external code memory.
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. X can be V
5. AH = Address high order byte
6. AL = Address low order byte
7. DI = Data Input, DO = Data Output, all other values are in hex.
8. SFAH[7:5] = 111b selects Block 1, SFAH[7] = 0b selects Block 0
9. Instruction must be located in Block 1 or external code memory.
SFCM[7] = 1: Interrupt enable for flash operation completion
SFCM[7] = 1: Interrupt enable for flash operation completion
9
9
9
9
9
9
9
9
9
4-6: IAP C
4-7: IAP C
3
3
5
5
5
0: polling enable for flash operation completion
IL
0: polling enable for flash operation completion
IL
or V
or V
5
8
IH
IH
9
9
, but no other value.
, but no other value.
OMMANDS
OMMANDS
1
1
SFCM [6:0]
SFCM [6:0]
FOR
FOR
0DH
0BH
0EH
0CH
0DH
0BH
0EH
0CH
01H
0FH
03H
05H
09H
08H
01H
0FH
03H
05H
09H
09H
08H
SST89E/V564RD
SST89E/V554RC
2
2
SFDT [7:0]
SFDT [7:0]
42
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
DO
55H
DO
55H
55H
55H
DI
DI
X
X
8
7
8
7
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
SFAH [7:0]
SFAH [7:0]
AAH
5AH
5AH
AH
55H
AH
55H
AH
AH
AH
AH
AH
AH
X
X
X
X
X
X
X
X
4
4
6
5
FlashFlex MCU
S71207-08-EOL
SFAL [7:0]
SFAL [7:0]
AL
AL
AL
AL
AL
AL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
T4-6.4 1207
T4-7.2 1207
1/07