24LC01BH-I/ST Microchip Technology, 24LC01BH-I/ST Datasheet - Page 11
![IC EEPROM 1KBIT 400KHZ 8TSSOP](/photos/6/59/65937/c04-086_st_sml.jpg)
24LC01BH-I/ST
Manufacturer Part Number
24LC01BH-I/ST
Description
IC EEPROM 1KBIT 400KHZ 8TSSOP
Manufacturer
Microchip Technology
Specifications of 24LC01BH-I/ST
Memory Size
1K (128 x 8)
Package / Case
8-TSSOP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Organization
128 K x 8
Interface Type
2-Wire
Maximum Clock Frequency
0.1 MHz
Access Time
3500 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3.3 V, 5 V
Memory Configuration
128 X 8
Clock Frequency
400kHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
TSSOP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
8.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
of read operations: current address read, random read
and sequential read.
8.1
The 24XX01 contains an address counter that
maintains the address of the last word accessed,
internally incremented by ‘
access (either a read or write operation) was to
address
would access data from address
the slave address with R/W bit set to ‘
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24XX01
discontinues transmission (Figure 8-1).
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX01 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal Address Pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘
24XX01 will then issue an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX01 discontinues transmission (Figure 8-2).
FIGURE 8-1:
© 2009 Microchip Technology Inc.
READ OPERATION
Current Address Read
n
Random Read
, the next current address read operation
Bus Activity
Master
SDA Line
Bus Activity
x = “don’t care”
CURRENT ADDRESS READ
1
’. There are three basic types
1
’. Therefore, if the previous
n + 1
S
A
R
S
T
T
. Upon receipt of
1
’, the 24XX01
1 0 1 0 x x x 1
1
’. The
Control
Byte
Select
Block
Bits
8.3
Sequential reads are initiated in the same way as a
random read, except that once the 24XX01 transmits
the first data byte, the master issues an acknowledge
(as opposed to a Stop condition in a random read). This
directs the 24XX01 to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24XX01 contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4
The 24XX01 employs a V
which disables the internal erase/write logic if the V
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
A
C
K
24AA01/24LC01B
Sequential Read
Noise Protection
Data (n)
CC
threshold detector circuit
N
C
A
K
o
P
S
O
P
T
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