93LC66BT-I/OT Microchip Technology, 93LC66BT-I/OT Datasheet - Page 8

• Manufacturer Part Number: 93LC66BT-I/OT
• Description: IC EEPROM 4KBIT 2MHZ SOT23-6
• Manufacturer: Microchip Technology

Specifications of 93LC66BT-I/OT

• Memory Size: 4K (256 x 16)
• Package / Case: SOT-23-6
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 256 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 2 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 93LC66BT-I/OT

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.6
The 93XX66A/B/C powers up in the ERASE/WRITE
Disable (EWDS) state. All Programming modes must be
preceded by an ERASE/WRITE Enable (EWEN) instruc-
tion. Once the EWEN instruction is executed, program-
ming remains enabled until an EWDS instruction is
executed or Vcc is removed from the device.
FIGURE 2-5:
FIGURE 2-6:
2.7
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (If ORG pin is low or A-Version
devices) or 16-bit (If ORG pin is high or B-version
FIGURE 2-7:
DS21795B-page 8
CLK
CLK
CS
DO
CS
DI
CLK
DI
CS
DI
ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)
READ
HIGH-Z
1
1
1
EWDS TIMING
EWEN TIMING
READ TIMING
1
0
0
0
0
0
An
0
1
•••
0
A0
1
0
Dx
X
X
•••
specified time delay (T
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all ERASE/
WRITE functions and should follow all programming
operations. Execution of a READ instruction is indepen-
dent of both the EWEN and EWDS instructions.
devices) output string. The output data bits will toggle on
the rising edge of the CLK and are stable after the
when CS is held high. The memory data will automati-
cally cycle to the next register and output sequentially.
•••
•••
D0
Dx
X
X
•••
T
T
CSL
CSL
D0
PD
 2003 Microchip Technology Inc.
). Sequential read is possible
Dx
•••
D0