24LC014-I/P Microchip Technology, 24LC014-I/P Datasheet - Page 11
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24LC014-I/P
Manufacturer Part Number
24LC014-I/P
Description
IC EEPROM 1KBIT 400KHZ 8DIP
Manufacturer
Microchip Technology
Specifications of 24LC014-I/P
Memory Size
1K (128 x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Clock Frequency
400kHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
DIP
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Svhc
No SVHC (15-Dec-2010)
Package /
RoHS Compliant
Memory Configuration
128 X 8
Interface Type
I2C, Serial, 2-Wire
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
24LC014I/P
8.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
The 24AA014/24LC014 contains an address counter
that maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n, the next
current address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/W bit set to ‘1’, the 24AA014/24LC014 issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 24AA014/24LC014
discontinues transmission
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24AA014/24LC014 as part of a write operation.
FIGURE 8-1:
2010 Microchip Technology Inc.
READ OPERATIONS
Current Address Read
Random Read
CURRENT ADDRESS READ
(Figure
Bus Activity
Master
SDA Line
Bus Activity
8-1).
S
A
R
T
T
S
Control
Byte
C
A
K
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again but with the R/W bit set to a ‘1’.
The 24AA014/24LC014 will then issue an acknowl-
edge and transmits the eight-bit data word. The master
will not acknowledge the transfer, but does generate a
Stop condition and the 24AA014/24LC014 discontin-
ues transmission
internal address counter will point to the address
location following the one that was just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24AA014/24LC014
transmits the first data byte, the master issues an
acknowledge as opposed to a Stop condition in a
random read. This directs the 24AA014/24LC014 to
transmit the next sequentially addressed 8-bit word
(Figure
To provide sequential reads the 24AA014/24LC014
contains an internal Address Pointer which is
incremented by one at the completion of each opera-
tion. This Address Pointer allows the entire memory
contents to be serially read during one operation. The
internal Address Pointer will automatically roll over
from address 07Fh to address 000h.
Data
24AA014/24LC014
8-3).
Sequential Read
O
K
N
A
C
O
P
S
T
P
(Figure
8-2). After this command, the
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