AT24C04B-TH-T Atmel, AT24C04B-TH-T Datasheet - Page 6
![IC EEPROM 4KBIT 1MHZ 8TSSOP](/photos/6/83/68331/453-8-tssop_sml.jpg)
AT24C04B-TH-T
Manufacturer Part Number
AT24C04B-TH-T
Description
IC EEPROM 4KBIT 1MHZ 8TSSOP
Manufacturer
Atmel
Datasheet
1.AT24C04B-PU.pdf
(28 pages)
Specifications of AT24C04B-TH-T
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
4K (512 x 8)
Speed
400kHz, 1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Density
4Kb
Interface Type
Serial (2-Wire)
Organization
512x8
Access Time (max)
900ns
Frequency (max)
400KHz
Write Protection
Yes
Data Retention
100Year
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Temp Range
-40C to 85C
Supply Current
3mA
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT24C04B-TH-T
Manufacturer:
Atmel
Quantity:
40
Company:
Part Number:
AT24C04B-TH-T
Manufacturer:
ATMEL
Quantity:
5 000
3.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see
start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see
STOP CONDITION:
command will place the EEPROM in a standby power mode (see
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C04B/08B features a low-power standby mode which is enabled:
2-WIRE SOFTWARE RESET: After
2-wire part can be reset by following these steps:
Figure 3.
AT24C04B/08B
SCL
SDA
(a) Upon power-up and
(b) After the receipt of the STOP bit and the completion of any internal operations.
(a) Create a start bit condition,
(b)
(c) Create another start bit followed by a stop bit condition as shown below. The device is ready for the next
communication after the above steps have been completed.
Clock 9 cycles,
Start bit
Software reset
Figure
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
7).
1
2
an
interruption
Dummy Clock Cycles
3
Figure 6
in
). Data changes during SCL high periods will indicate a
protocol,
Figure
8
7).
power
9
loss
Start bit
or
system
5226G–SEEPR–11/09
reset,
Stop bit
any