AT25080B-SSHL-B Atmel, AT25080B-SSHL-B Datasheet - Page 9

• Manufacturer Part Number: AT25080B-SSHL-B
• Description: IC EEPROM 8KBIT 20MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25080B-SSHL-B

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 8K (1K x 8)
• Speed: 5MHz, 10MHz, 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 1024 X 8
• Interface Type: Serial, SPI
• Clock Frequency: 20MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5228D–SEEPR–4/10
WRITE SEQUENCE (WRITE): In order to program the AT25080B/160B, two separate instructions must be exe-
cuted. First, the device must be write enabled via the WREN instruction. Then a write (WRITE) instruction may be
executed. Also, the address of the memory location(s) to be programmed must be outside the protected address
field location selected by the block write protection level. During an internal write cycle, all commands will be
ignored except the RDSR instruction.
A write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE
op-code is transmitted via the SI line followed by the byte address (A15
grammed (see
CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
The AT25080B/160B is capable of a 32-byte page write operation. After each byte of data is received, the five low-
order address bits are internally incremented by one; the high-order bits of the address will remain constant. If
more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25080B/160B is automatically returned to the write disable state at the completion of a write
cycle.
Note:
Table 3-6.
If the device is not write-enabled (WREN), the device will ignore the write instruction and will return to the standby
state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.
Don’t Care Bits
Address
Address Key
A
Table
N
3-6). Programming will start after the CS pin is brought high. The low-to-high transition of the
AT25080B
A
A
15
9
–A
–A
0
10
AT25160B
A
–
A
A0) and the data (D7
15
10
–A
–A
11
0
AT25080B/160B
–
D0) to be pro-
9