24LC21AT/SN Microchip Technology, 24LC21AT/SN Datasheet - Page 12

• Manufacturer Part Number: 24LC21AT/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC21AT/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24LC21A
7.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
The 24LC21A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LC21A
issues an acknowledge and transmits the eight-bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21A
discontinues transmission (Figure 7-1).
FIGURE 7-1:
7.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21A as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC21A will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC21A
discontinues transmission (Figure 7-2).
DS21160G-page 12
Bus Activity
Master
SDA Line
Bus Activity
READ OPERATION
Current Address Read
Random Read
S
T
A
R
T
S
1 0 1 0 0 0 0 1
CURRENT ADDRESS
READ
Control
Byte
C
A
K
Data n
N
O
C
A
K
S
T
O
P
P
7.3
Sequential reads are initiated in the same way as a
random read except that after the 24LC21A transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LC21A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC21A contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4
The 24LC21A employs a V
which disables the internal erase/write logic if the V
is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Sequential Read
Noise Protection
© 2008 Microchip Technology Inc.
CC
threshold detector circuit
CC