25AA040-I/SN Microchip Technology, 25AA040-I/SN Datasheet - Page 6

• Manufacturer Part Number: 25AA040-I/SN
• Description: IC EEPROM 4KBIT 1MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25AA040-I/SN

• Memory Size: 4K (512 x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 1MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 512 X 8 / 256 X 16
• Ic Interface Type: SPI
• Clock Frequency: 1MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 5AA040-I/SNG; 5AA040-I/SNG

25AA040/25LC040/25C040
2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go in Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes into the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
2.2
The SO pin is used to transfer data out of the 25XX040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3
This pin is a hardware write-protect input pin. When
WP is low, all writes to the array or STATUS register
are disabled, but any other operation functions
normally. When WP is high, all functions, including
nonvolatile writes operate normally. WP going low at
any time will reset the write enable latch and inhibit
programming, except when an internal write has
already begun. If an internal write cycle has already
begun, WP going low will have no effect on the write.
See Table 3-3 for Write-Protect Functionality Matrix.
DS21204E-page 6
HOLD
Name
SCK
V
V
WP
SO
CS
SI
SS
CC
PIN DESCRIPTIONS
Chip Select (CS)
Serial Output (SO)
Write-Protect (WP)
PDIP
1
2
3
4
5
6
7
8
SOIC
PIN FUNCTION TABLE
1
2
3
4
5
6
7
8
TSSOP
3
4
5
6
7
8
1
2
Chip Select Input
Serial Data Output
Write-Protect Pin
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Description
2.4
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5
The SCK is used to synchronize the communication
between a master and the 25XX040. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6
The HOLD pin is used to suspend transmission to the
25XX040 while in the middle of a serial sequence
without having to retransmit the entire sequence again
at a later time. It must be held high any time this func-
tion is not being used. Once the device is selected and
a serial sequence is underway, the HOLD pin may be
pulled low to pause further serial communication
without resetting the serial sequence. The HOLD pin
must be brought low while SCK is low, otherwise the
HOLD function will not be invoked until the next SCK
high-to-low transition. The 25XX040 must remain
selected during this sequence. The SI, SCK and SO
pins are in a high-impedance state during the time the
part is paused and transitions on these pins will be
ignored. To resume serial communication, HOLD must
be brought high while the SCK pin is low, otherwise
serial communication will not resume. Lowering the
HOLD line at any time will tri-state the SO line.
Serial Input (SI)
Serial Clock (SCK)
Hold (HOLD)
© 2006 Microchip Technology Inc.