AT88SC25616C-SU Atmel, AT88SC25616C-SU Datasheet - Page 3
![IC EEPROM 256KBIT 1.5MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
AT88SC25616C-SU
Manufacturer Part Number
AT88SC25616C-SU
Description
IC EEPROM 256KBIT 1.5MHZ 8SOIC
Manufacturer
Atmel
Series
CryptoMemory®r
Specifications of AT88SC25616C-SU
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
256K (32K x 8)
Speed
5MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
For Use With
AT88SC-SDK1 - KIT TUEMA DK CRYPTOMEM SMARTCARDAT88SC-DK1 - KIT DEV FOR AT88SCXXXXC FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT88SC25616C-SU C0090
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT88SC25616C-SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
2.
2.1.
2.2.
2.3.
2.4.
5017KJS–SMEM–08/09
Figure 2.
SCL/CLK
Pin Descriptions
Supply Voltage (V
The V
Clock (SCL/CLK)
In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency f. The
nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/ f. When the
synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge
clock data out of the device.
Reset (RST)
The AT88SC25616C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset
sequence is activated, the device will output the data programmed into the 64-bit answer-to-reset register. An internal
pull-up on the RST input pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC25616C does not support the synchronous answer-to-reset sequence.
Serial Data (SDA/IO)
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of
other open drain or open collector devices. An external pull-up resistor should be connected between SDA and VCC.
The value of this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This
rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher
frequency operations while drawing higher average power. SDA/IO information applies to both asynchronous and
synchronous protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and
negative edge clock data out of the device.
SDA/IO
GND
V
CC
RST
CC
input is a 2.7V to 5.5V positive voltage supplied by the host.
Block Diagram
CC
Asynchronous
ISO Interface
Management
Synchronous
)
Reset Block
Interface
Power
Certification Unit
Answer to Reset
Encryption and
Authentication,
Data Transfer
Verification
Password
Generator
EEPROM
Random
AT88SC25616C
3