AT25DQ161-SSH-B Atmel, AT25DQ161-SSH-B Datasheet
AT25DQ161-SSH-B
Specifications of AT25DQ161-SSH-B
Related parts for AT25DQ161-SSH-B
AT25DQ161-SSH-B Summary of contents
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... Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil and 208-mil wide) – 8-pad Ultra Thin DFN ( 0.6 mm) 16-Megabit 2.7-volt Minimum SPI Serial Flash Memory with Dual-I/O and Quad-I/O Support AT25DQ161 Preliminary 8671A–DFLASH–07/09 ...
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... Description The AT25DQ161 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DQ161, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices ...
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Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Symbol Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode ...
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... WP (I GND 4 5 AT25DQ161 [Preliminary The WP# pin controls the hardware locking feature of the data to be clocked in on 3-0 ) and, when used with other pins, allows four bits (on I data to be clocked in on 3-0 ) and, when used with other pins, allows four bits (on I/O ...
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... Memory Array To provide the greatest flexibility, the memory array of the AT25DQ161 can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into phys- ical sectors of uniform size, of which each sector can be individually protected from program and erase operations ...
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... Figure 4-1. Memory Architecture Diagram AT25DQ161 [Preliminary] 6 8671A–DFLASH–07/09 ...
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... Device Operation The AT25DQ161 is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the SPI Master. The SPI Master communicates with the AT25DQ161 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO) ...
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... All opcode, address, and data bytes are trans- ferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DQ161 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...
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... Following the three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode is used for the Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the 8671A– ...
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... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array – 1Bh Opcode SCK OPCODE MSB MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DQ161 [Preliminary ADDRESS BITS A23-A0 DON'T CARE MSB ADDRESS BITS A23- MSB ...
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... I/O 1 after every four clock cycles. When the last byte (1FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. ...
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... No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin will terminate the read operation and put the I/O impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. AT25DQ161 [Preliminary ...
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... Status Register to a logical “1” state. To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer ...
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... Status Register. Figure 8-1. Byte Program SCK MSB HIGH-IMPEDANCE SO Figure 8-2. Page Program SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DQ161 [Preliminary only programming a single byte “Sector Lockdown” on page or t time to determine if the data bytes have finished programming OPCODE ADDRESS BITS A23- ...
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... CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be pro- grammed into the memory array. In addition, if the address specified by A23-A0 points to a memory location within a sector that is in the protected state (see ...
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... After the address bytes have been clocked in, data can then be clocked into the device four bits at a time on the I/O AT25DQ161 [Preliminary time to determine if the data bytes have finished programming. ...
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... CS pin is deasserted, and the CS pin must be deasserted on byte boundaries (multi- ples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by A23-A0 points to a memory loca- tion within a sector that is in the protected state down (See “ ...
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... WEL bit of the Status Reg- ister to a logical “1” state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three AT25DQ161 [Preliminary ...
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... If the address specified by A23-A0 points to a memory location within a sector that is in the pro- tected or locked down state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “ ...
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... Since the need to suspend a program or erase operation is immediate, the Write Enable com- mand does not need to be issued prior to the Program/Erase Suspend command being issued. AT25DQ161 [Preliminary CHPE time to determine if the device has finished erasing. At ...
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Therefore, the Program/Erase Suspend command operates independently of the state of the WEL bit in the Status Register. To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of B0h must be clocked into the ...
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... Write Status Register (All Opcodes) Read Configuration Register Write Configuration Register Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down AT25DQ161 [Preliminary] 22 Operations Allowed and Not Allowed During a Program or Erase Suspend Operation During Operation During Program Suspend Erase Suspend Allowed ...
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... Program/Erase Resume The Program/Erase Resume command allows a suspended program or erase operation to be resumed and continue programming a Flash page or erasing a Flash memory block where it left off. As with the Program/Erase Suspend command, the Write Enable command does not need to be issued prior to the Program/Erase Resume command being issued. Therefore, the Pro- gram/Erase Resume command operates independently of the state of the WEL bit in the Status Register ...
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... Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. AT25DQ161 [Preliminary ...
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Write Disable The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg- ister to the logical "0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, ...
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... CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”. AT25DQ161 [Preliminary] 26 Protect Sector ...
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... Sectors that have been erase or program suspended must remain in the unprotected state Global Protect operation is attempted while a sector is erase or program suspended, the protec- tion operation will abort, the protection states of all sectors in the Flash memory array will not change, and WEL bit in the Status Register will be reset back to a logical “0”. ...
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... Status Register will perform a Global Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an FFh if software-lock- ing or hardware-locking is desired along with the Global Protect. AT25DQ161 [Preliminary] 28 Valid SPRL and Global Protect/Unprotect Conditions ...
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If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro- tect, then the system can simply write a 0Fh to the first byte of the Status Register to change the SPRL bit ...
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... When changing the SPRL bit to a logical “1” from a logical “0” also possible to perform a Global Protect or Global Unprotect at the same time by writing the appropriate values into bits and 2 of the first byte of the Status Register. Tables 9-4 AT25DQ161 [Preliminary] 30 Read Sector Protection Register 0 1 ...
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Table 9-4. (Don't Care) Note: Table 9- 8671A–DFLASH–07/09 Sector Protection Register States Sector Protection Register “n” represents a sector number Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be ...
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... As a safeguard against accidental or erroneous locking down of sectors, the Sector Lockdown command can be enabled and disabled as needed by using the SLE bit in the Status Register. In addition, the current sector lockdown state can be frozen so that no further modifications to AT25DQ161 [Preliminary] 32 Sector Lockdown Register Values Sector Lockdown Status Sector is not locked down and can be programmed and erased ...
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Sector Lockdown Registers can be made (see the Sector Lockdown command is disabled or if the sector lockdown state is frozen, then any attempts to issue the Sector Lockdown command will be ignored, and the device will reset the ...
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... Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped- ance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 10-3. Read Sector Lockdown Register SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DQ161 [Preliminary OPCODE ADDRESS BITS A23- MSB ...
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... Once these 64 bytes have been programmed, they cannot be erased or reprogrammed. The remaining 64 bytes of the OTP Security Register (byte locations 64 through 127) are factory programmed by Atmel and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. ...
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... After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been read, the device will continue reading back at AT25DQ161 [Preliminary ...
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No delays will be incurred when wrapping around from the end of the register to the beginning of the register. Deasserting the CS pin will terminate the read operation and put the SO pin ...
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... Write Enable Latch Status 0 RDY/BSY Ready/Busy Status Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command. 2. R/W = Readable and writeable R = Readable only AT25DQ161 [Preliminary] 38 (2) Type Description 0 Sector Protection Registers are unlocked (default). R/W 1 Sector Protection Registers are locked ...
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Table 11-2. Status Register Format – Byte 2 (1) Bit Name 7 RES Reserved for future use 6 RES Reserved for future use 5 RES Reserved for future use 4 RSTE Reset Enabled 3 SLE Sector Lockdown Enabled 2 PS ...
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... In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, Write Status Register, or Write Configuration Register command must have been clocked into the device. AT25DQ161 [Preliminary] 40 8671A–DFLASH–07/09 ...
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RSTE Bit The RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the log- ical “0” state (the default state after power-up), the Reset command is disabled and any attempts to ...
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... SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 11-3. Bit 7 SPRL AT25DQ161 [Preliminary ...
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Figure 11-2. Write Status Register Byte 1 11.3 Write Status Register Byte 2 The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Sta- tus Register. Using the Write Status Register Byte ...
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... Table 11-5. Configuration Register Format (1) Bit Name 7 QE Quad Enable 6:0 RES Reserved for future use Notes: 1. Only bit 7 of the Configuration Register will be modified when using the Write Configuration Register command. 2. R/W = Readable and writeable R = Readable only AT25DQ161 [Preliminary SCK OPCODE ...
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... Read Array commands are disabled and will not be recognized by the device as valid com- mands, and the should be externally pulled-high to avoid erroneous or unwanted device operation. The Reset command has no effect on the QE bit. The QE bit defaults to the logical “0” state when devices are initially shipped from Atmel. Figure 11-4. Read Configuration Register CS SCK ...
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... The remaining pages in the 64-Kbyte sector will retain their previous contents. The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. AT25DQ161 [Preliminary ...
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... The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven- dor specific Extended Device Information ...
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... HIGH-IMPEDANCE SO Note: Each transition 12.3 Deep Power-Down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep AT25DQ161 [Preliminary] 48 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JEDEC Assigned Code ...
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Power-Down command offers the ability to place the device into an even lower power consump- tion state called the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will ...
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... Hold mode won’t end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. AT25DQ161 [Preliminary ...
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... SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the AT25DQ161 a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
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... D. Last bit of BYTE A is clocked out from the Master. E. Last bit of BYTE A is clocked into the slave. F. Slave clocks out first bit of BYTE B. G. Master clocks in first bit of BYTE B. H. Slave clocks out second bit of BYTE B. I. Master clocks in last bit of BYTE B. AT25DQ161 [Preliminary ...
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... CC all inputs at CMOS levels f = 100 MHz mA; OUT Max MHz mA; OUT Max MHz mA; OUT Max MHz mA; OUT Max MHz mA; OUT Max MHz mA; OUT Max Max Max CMOS levels IN AT25DQ161 -40°C to 85°C 2.7V to 3.6V Min Typ Max Units µA µ µA 53 ...
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... Output Disable Time DIS (2) t Output Valid Time V t Output Hold Time OH t HOLD Low Setup Time (relative to Clock) HLS t HOLD Low Hold Time (relative to Clock) HLH AT25DQ161 [Preliminary] 54 Condition V = CMOS levels OUT I = 1.6 mA Min -100 µ Min OH CC Maximum Clock Frequencies ...
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AC Characteristics – All Other Parameters (Continued) Symbol Parameter t HOLD High Setup Time (relative to Clock) HHS t HOLD High Hold Time (relative to Clock) HHH (1) t HOLD Low to Output High-Z HLQZ (1) t HOLD High ...
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... Power-up Device Delay Before Program or Erase Allowed PUW V Power-on Reset Voltage POR 14.8 Input Test Waveforms and Measurement Levels DRIVING LEVELS 14.9 Output Test Load DEVICE UNDER AT25DQ161 [Preliminary 0.1V CC < (10% to 90%) F TEST 15 pF (frequencies above 70 MHz) or 30pF Min 70 1 ...
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AC Waveforms Figure 15-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 15-2. Serial Output Timing CS SCK Figure 15-3. WP Timing for Write Status Register Byte 1 Command ...
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... Figure 15-4. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO Figure 15-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI t HLQZ SO AT25DQ161 [Preliminary HHH HLS t HLH t HLS t HLH t HHQX t HHS t HHS 8671A–DFLASH–07/09 ...
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... Interface 1 = Serial 16.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Ordering Code Package AT25DQ161-MH-Y 8MA1 AT25DQ161-MH-T AT25DQ161-SSH-B 8S1 AT25DQ161-SSH-T AT25DQ161-SH-B 8S2 AT25DQ161-SH-T Note: The shipping carrier option code is not marked on the devices. 8MA1 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) 8S1 8-lead, 0.150” ...
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... UDFN E Pin TOP VIEW Pin #1 Notch (0.20 R) (Option BOTTOM VIEW L Package Drawing Contact: packagedrawings@atmel.com AT25DQ161 [Preliminary] 60 SIDE VIEW A1 A 0.45 Option A 1 Pin #1 Chamfer (C 0.35) SYMBOL TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead ...
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JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO ...
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... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com AT25DQ161 [Preliminary TOP VIEW ...
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Revision History Revision Level – Release Date A – July 2009 8671A–DFLASH–07/09 History Initial release. 63 ...
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