25LC512-E/P Microchip Technology, 25LC512-E/P Datasheet - Page 14
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25LC512-E/P
Manufacturer Part Number
25LC512-E/P
Description
IC EEPROM 512KBIT 20MHZ 8DIP
Manufacturer
Microchip Technology
Datasheet
1.25LC512-ISM.pdf
(36 pages)
Specifications of 25LC512-E/P
Memory Size
512K (64K x 8)
Package / Case
8-DIP (0.300", 7.62mm)
Operating Temperature
-40°C ~ 125°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
20MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Organization
64 K x 8
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Access Time
50 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
7 mA
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
25LC512-E/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
25LC512
2.8
The PAGE ERASE instruction will erase all bits (FFh)
inside the given page. A Write Enable (WREN) instruc-
tion must be given prior to attempting a PAGE ERASE.
This is done by setting CS low and then clocking out
the proper instruction into the 25LC512. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The PAGE ERASE instruction is entered by driving CS
low, followed by the instruction code (Figure 2-8) and
two address bytes. Any address inside the page to be
erased is a valid address.
FIGURE 2-8:
DS22065C-page 14
PAGE ERASE
SCK
SO
CS
SI
PAGE ERASE SEQUENCE
0
0
1
1
0
Instruction
2
0
3
0
4
0
5
High-Impedance
1
6
0
7
15 14 13 12
8
CS must then be driven high after the last bit of the
address or the PAGE ERASE will not execute. Once
the CS is driven high the self-timed PAGE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the PAGE ERASE cycle
is complete.
If a PAGE ERASE instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
9 10 11
16-bit Address
21 22 23
2
2010 Microchip Technology Inc.
1
0
ERASE