AT25DF641-S3H-B Atmel, AT25DF641-S3H-B Datasheet - Page 43

• Manufacturer Part Number: AT25DF641-S3H-B
• Description: IC FLASH 64MBIT 100MHZ 16SOIC
• Manufacturer: Atmel

Specifications of AT25DF641-S3H-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (32K pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Architecture: Sectored
• Interface Type: SPI Serial
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 19 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 128
• Memory Configuration: 32K Pages X 256 Bytes
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 5ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3.
3680F–DFLASH–4/10
Deep Power-Down
During normal operation, the device will be placed in the standby mode to consume less power as long as the
pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the
ability to place the device into an even lower power consumption state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command
will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be
ignored, the mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the
B9h, and then deasserting the
ignored. When the
time of t
The complete opcode must be clocked in before the
an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the
standby mode once the
power-cycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase
cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation
has been completed in order for the device to enter the Deep Power-Down mode.
Figure 11-3. Deep Power-Down
SCK
SO
CS
I
SI
CC
EDPD
.
S tandby Mode C urrent
CS
MS B
HIG H-IMP E DANC E
1
0
Active C urrent
pin is deasserted, the device will enter the Deep Power-Down mode within the maximum
0
1
CS
1
2
OP C ODE
1
3
pin is deasserted. In addition, the device will default to the standby mode after a
1
4
CS
0
5
Deep P ower-Down Mode C urrent
0
6
pin. Any additional data clocked into the device after the opcode will be
1
7
t
E DP D
CS
pin is deasserted, and the
Atmel AT25DF641
CS
CS
pin, clocking in the opcode of
pin must be deasserted on
CS
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