TWR-P1025 Freescale Semiconductor, TWR-P1025 Datasheet
TWR-P1025
Specifications of TWR-P1025
Related parts for TWR-P1025
TWR-P1025 Summary of contents
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... TWR-P1025 Tower Module Hardware User Guide TWR-P1025HUG Rev. 2, 4/2012 ...
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... Chaoyang District Beijing 100022 China +86 010 5879 8000 support.asia@freescale.com Document Number: TWR-P1025HUG Rev. 2, 4/2012 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...
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... Micro Secure Digital Card Slot (micro SDHC)............................................................... 3-8 3.10 Local Bus Interface .......................................................................................................... 3-8 3.11 UART............................................................................................................................... 3-8 3.12 I2C ................................................................................................................................... 3-9 3.13 SPI.................................................................................................................................... 3-9 3.14 DDR3 ............................................................................................................................... 3-9 3.15 GPIO & Interrupts ......................................................................................................... 3-12 4.1 P1025 Jumper Table......................................................................................................... 4-1 Freescale Semiconductor Contents Title Chapter 1 TWR-P1025 Overview Chapter 2 Power Requirements Chapter 3 Hardware Description Chapter 4 Switch Table TWR-P1025 Hardware User Guide, Rev. 2 Page Number iii ...
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... Number Input/Output Connectors and Pin Usage Table 5.1 LED Usage....................................................................................................................... 5-1 5.2 I/O Connectors and Pin Usage Table ............................................................................... 5-1 6.1 Overview.......................................................................................................................... 6-1 A.1 Version Number 2 ............................................................................................................ 7-1 A.2 Version Number 1 ............................................................................................................ 7-1 A.3 Version Number 0 ............................................................................................................ 7-1 iv Contents Title Chapter 5 Chapter 6 Tower Elevator Connections Appendix A Revision History TWR-P1025 Hardware User Guide, Rev. 2 Page Number Freescale Semiconductor ...
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... Figure Number 1-1 Freescale Tower System.......................................................................................................... 1-1 1-2 Callouts on front side of the TWR-P1025 .............................................................................. 1-3 1-3 Callouts on back side of the TWR-P1025............................................................................... 1-3 2-1 Power Supply Barrel Connector (J2) Polarity......................................................................... 2-1 3-1 TWR-P1025 Block Diagram................................................................................................... 3-1 3-2 P1025 Clocking Scheme ......................................................................................................... 3-3 3-3 eTSEC connection to AR8035 PHY ....................................................................................... 3-6 3-4 NOR Local Bus Connection ................................................................................................... 3-8 Freescale Semiconductor Figures Title TWR-P1025 Hardware User Guide, Rev. 2 ...
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... I2C2 Connectivity ................................................................................................................... 3-9 3-9 DDR3 Signals ....................................................................................................................... 3-10 3-10 P1025 Interrupt Usage .......................................................................................................... 3-13 3-11 P1025 GPIO Usage ............................................................................................................... 3-13 4-1 P1025 Jumper Table................................................................................................................ 4-1 5-1 LED Usage Table .................................................................................................................... 5-1 5-2 I/O Connectors and Pin Usage Table ...................................................................................... 5-1 6-1 TWR-P1025 Primary Connector Pinout ................................................................................. 6-1 6-2 TWR-P1025 Primary Connector Pinout ................................................................................. 6-4 Freescale Semiconductor Tables Title Tables TWR-P1025 Hardware User Guide, Rev. 2 Page Number vii ...
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... The TWR-P1025 features the QorIQ P1025 dual core processor based on the PowerPC® e500 core architecture. The TWR-P1025 is available as a stand-alone product or can be combined with the Tower Elevator Modules (TWR-ELEV) and other Tower eco-system components to create development platforms for a wide variety of applications ...
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... Two (2) USB2.0 Type A • One (1) mini-USB TypeB dual UART • 512 MB DDR3@667 MHz • Flash • IEEE1588 pinned to header + DAC and VXCO (DNP option) Figure 1-2 and Figure 1-3 show the TWR-P1025 with some of the key features. 2 TWR-P1025 Hardware User Guide, Rev. 2 Freescale Semiconductor ...
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... Figure 1-2. Callouts on front side of the TWR-P1025 Figure 1-3. Callouts on back side of the TWR-P1025 Freescale Semiconductor TWR-P1025 Hardware User Guide, Rev. 2 TWR-P1025 Overview 3 ...
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... Follow the printed Quick Start Guide or the interactive DVD contained in the TWR-P1025 box for recommended get started steps. 1.5 QorIQ P1025 Device Notification The TWR-P1025 may be populated with either of the following QorIQ P1025 part numbers as indicated on a sticker on the underside of the module: • P1025NSN5DFB, which is a non-encrypted, standard temperature device, or • ...
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... TWR peripherals, the TWR-P1025 provides 5V and 3.3V supplies. There are several expansion options on the board that allow external boards to interface to the TWR-P1025, such as the mini PCIe connector, USB ports and elevator expansion. As these plug in cards have variable power requirements as well as numerous population combinations the Power capability of ...
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... Chapter 3 Hardware Description The TWR-P1025 is a Tower Controller Module featuring the P1025-a dual core e500v2 based microprocessor in a 561 TEPBGA package with a maximum core operating frequency of 533MHz intended to be used stand-alone or in the Freescale Tower System. Power is supplied through a 5V barrel connector ...
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... The CCB clock is used by virtually all of the synchronous system logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB 2 TWR-P1025 Hardware User Guide, Rev. 2 Figure 3-1, the SYSCLK Freescale Semiconductor ...
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... Table 3-2 describe the CCB and core platform frequency ratio selection. the DDRCLK input ratio to DDR controller clock ratio. The DDR runs at a fixed x10 multiplier to DDR_CLK. Freescale Semiconductor Figure 3-2. P1025 Clocking Scheme TWR-P1025 Hardware User Guide, Rev. 2 Hardware Description Table 3-3 describes 3 ...
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... Table 3-3. P1025 DDR Clock PLL Ratio Reset Configuration Value Name cfg_ddr_pll[0:2] Table 3-4. CPU Speed Selection CORE(0 &1) Speed QE Speed (MHz) (MHz) 533 TWR-P1025 Hardware User Guide, Rev. 2 CCB Clock : SYSCLK Ratio 4:1 5:1 6:1 e500 Core: CCB Clock Ratio Reserved Reserved 1:1 3:2 (1.5:1) 2:1 5:2 (2.5:1) ...
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... System Power The TWR-P1025 is powered through a barrel connector that provides 5V to the board (and elevators if present). All further operating voltages are generated via onboard regulators. The power supply should be rated at 5V @5A. 3.4 Debug Interface There are two JTAG connectors on board, one for the P1025 (J3) and another for the CPLD(J1). Both use standard debuggers available from Freescale and Altera respectively ...
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... AC24 Input RX data bit AE23 Input RX data bit AG22 Input RX data bit AE24 Input RX data bit AE25 Input RX data valid/error AE26 Input RX clock TWR-P1025 Hardware User Guide, Rev. 2 AR8035 AR8035 Pin Signal CLK_25M NA TXD3 37 TXD2 36 TXD1 35 TXD0 34 TX_CTL 32 TX_CLK 33 RXD3 25 ...
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... Input RX data bit AC20 Input RX data bit AC23 Input RX data bit AF27 I/O valid/error AD24 Input AG19 Output Management AF19 I/O Management TWR-P1025 Hardware User Guide, Rev. 2 Hardware Description AR8035 AR8035 Pin Signal MDC 40 clock MDIO 39 data AR8035 AR8035 Pin Signal - 23 eTSEC3 TXD3 37 ...
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... Both ports 3 & 4 can provide 5V@500mA to peripheral USB devices. 3.9 Micro Secure Digital Card Slot (micro SDHC) A micro Secure Digital (SD) card slot is available on the TWR-P1025 connected to the SD Host Controller (SDHC) signals of the P1025. Refer to Table 13 "I/O Connectors and Pin Usage Table" for the SDHC signal connection details. ...
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... I2C devices attached to each bus. Table 3-7. I2C1 Connectivity Device M24256-BWDW6TP 2K EEPROM (16-bit address) Table 3-8. I2C2 Connectivity Device MMA8451Q 3 Axis accelerometer GPIO expander AT24C01B 1K Board EEPROM (8-bit address) Primary elevator miniPCIe Slot Table 3-9. TWR-P1025 Hardware User Guide, Rev. 2 Hardware Description 9 ...
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... CS CS ODT ODT LDQS+/- UDQS+/- LDQS+/- UDQS+/- LDM UDM LDM UDM DQ[7:0] DQ[15:8] DQ[7:0] DQ[15:8] TWR-P1025 Hardware User Guide, Rev. 2 Termination/ Description Notes 47 Ohm to VTT Address bus 47 Ohm to VTT Bank Address Bus 47 Ohm to VTT Write Enable 47 Ohm to VTT Column Address Strobe 47 Ohm to VTT Row Address ...
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... Freescale Semiconductor Table 3-9. DDR3 Signals (continued) DDR3 Device 1 DDR3 Device 2 Signal Signal MCK0+/- MCK0+/- NC NC RESET RESET TWR-P1025 Hardware User Guide, Rev. 2 Hardware Description Termination/ Description Notes Clock/compleme nt 240 Ohm to ZQ calibration VSSQ (GND) Half Strength Driver calibration mode 40ohm to ...
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... DDR_CDR_1 reg ${DDR_CONT_GROUP}DDRCDR_1 = 0x00000000 # DDR_CDR_2 reg ${DDR_CONT_GROUP}DDRCDR_2 = 0x00000000 #delay before enable wait 500 # DDR_SDRAM_CFG reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG = 0xc70c0000 #wait for DRAM data initialization wait 2000 3.15 GPIO & Interrupts Table 3-10 lists external interrupt sources of P1025. 12 TWR-P1025 Hardware User Guide, Rev. 2 Freescale Semiconductor ...
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... Primary elevator GPIO9 Primary elevator GPIO14 Primary elevator GPIO15 Primary elevator GPIO16 Secondary elevator GPIO27/J4.13 Secondary elevator GPIO28/J4.15 Secondary elevator GPIO17/J4.17 Secondary elevator GPIO26/J4.16 Primary elevator GPIO4/J4.18 Primary elevator GPIO6/J4.20 Unused/CPLD Unused/CPLD LED D2 LED D3 TWR-P1025 Hardware User Guide, Rev. 2 Hardware Description 13 ...
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... Chapter 4 Switch Table 4.1 P1025 Jumper Table There are several switches on the TWR-P1025 that provide configuration selection and signal isolation (Table 4-1). The default switch settings are shown in red. Settings Feature [OFF=1 ON=0] S1.1 OFF ON S1.2 OFF ON S1.3 OFF ON S1.4 OFF ON S1.5 OFF ON S1.6 OFF ON S1.7 S1.8 NOTE: All other switch settings are reserved. ...
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... Green – 100Mbps Green ON – Link Blink - Activity Green/Orange Orange - 1000Mbps Green – 100Mbps Port Pin J8.1 J8.2 J8.3 TWR-P1025 Hardware User Guide, Rev. 2 LED Off Off for no Activity User programmable User programmable 3V3 Power OFF ASLEEP Status No Link 10Mbps No Link 10Mbps Pin Function ...
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... CN1.7 CN1.8 CN1.9 CN1.10 CN1.11 CN1.12 CN1.13 CN1.14 - J3.1 J3.2 J3.3 J3.4 J3.5 J3.6 J3.7 J3.8 J3.9 J3.10 J3.11 J3.12 J3.13 J3.14 TWR-P1025 Hardware User Guide, Rev. 2 Pin Function N/C Ground SDHC_D2 SDHC_D3 SDHC_CMD +3.3V SDHC_CLK Ground SDHC_D0 SDHC_D1 SD Card Detect (inverted polarity) +3V3 Ground Ground Ground Ground BOARD RESET Test Data In - Test Data Out Test Reset ...
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... J1.10 J4.1 J4.2 J4.3 J4.4 J4.5 J4.6 J4.7 J4.8 J4.9 J4.10 J4.11 J4.12 J4.13 J4.14 J4.15 J4.16 J4.17 J4.18 J4.19 J4.20 TWR-P1025 Hardware User Guide, Rev. 2 Input/Output Connectors and Pin Usage Table Pin Function Checkstop Out Ground Test CLK Ground Test Data Out Power Test Mode Select - - - Test Data In Ground Ground Power UCC7 RXD0 UCC3 RXD0 UCC7 TXD0 UCC3 RXD0 UCC7 RTS_B ...
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... Port Pin J7.1 J7.2 J7.3 J7.4 J7.5 J7.6 J7.7 J7.8 J5.1 J5.2 J5.3 J5.4 J5.5 J5.6 J5.7 J5.8 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 P2.16 P2.17 TWR-P1025 Hardware User Guide, Rev. 2 Pin Function 1588 CLK_IN 1588_PULSE_OUT2 1588_PULSE_OUT1 1588_CLK_OUT 1588_TRIGIN2 1588_ALARM_OUT1 1588_TRIGIN1 1588_ALARM_OUT2 5V Out USB3_DN USB3_DP Ground 5V Out USB4_DN USB4_DP Ground Pull up to +3.3V Power Reserved Ground Reserved Power - Reserved Ground Reserved MPCIE_CLK_N Reserved MPCIE_CLK_P Reserved Ground Reserved ...
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... P2.18 P2.19 P2.20 P2.21 P2.22 P2.23 P2.24 P2.25 P2.26 P2.27 P2.28 P2.29 P2.30 P2.31 P2.32 P2.33 P2.34 P2.35 P2.36 P2.37 P2.38 P2.39 P2.40 P2.41 P2.42 P2.43 P2.44 P2.45 P2.46 P2.47 P2.48 P2.49 P2.50 TWR-P1025 Hardware User Guide, Rev. 2 Input/Output Connectors and Pin Usage Table Pin Function Ground Reserved Reserved Ground RST_PCIE_N PCIE_RX0_N Power PCIE_RX0_P Ground Ground Power Ground I2C_SCL PCIE_TX0_N I2C_SDA PCIE_TX0_P Ground Ground USB2_DM Reserved USB2_DP Reserved Ground Reserved - Reserved - Reserved - Reserved Power ...
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... Input/Output Connectors and Pin Usage Table Table 5-2. I/O Connectors and Pin Usage Table (continued) Feature Connection RSV +3.3V 6 Port Pin P2.51 P2.52 TWR-P1025 Hardware User Guide, Rev. 2 Pin Function Reserved Power Freescale Semiconductor ...
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... Tower system. The Primary Connector (comprised of sides A and B) is utilized by the TWR-P1025 while the Secondary Connector (comprised of sides C and D) makes connections to the the SER3 & 7 Serial ports as well as ENET5 RMII and three SERDES lanes. Table 14 provides the pinout for the Primary Connector ...
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... Tower Elevator Connections Table 6-1. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B B15 ETH_TXEN B16 ETH_TXER B17 ETH_TXD3 B18 ETH_TXD2 B19 ETH_TXD1 B20 ETH_TXD0 B21 GPIO1 / RTS1 GPIO_EXPAN B22 GPIO2 / SDHC_D1 B23 GPIO3 B24 CLKIN0 B25 CLKOUT1 B26 GND B27 AN7 B28 ...
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... Table 6-1. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B B44 SPI0_MISO B45 SPI0_MOSI B46 SPI0_CS0_b B47 SPI0_CS1_b B48 SPI0_CLK B49 GND B50 SCL1 B51 SDA1 B52 GPIO5 / SD_CARD_D ET B53 USB0_DP_P DOWN B54 USB0_DM_P DOWN B55 IRQ_H B56 IRQ_G B57 IRQ_F B58 IRQ_E ...
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... Tower Elevator Connections Table 6-1. TWR-P1025 Primary Connector Pinout (continued) Pin# Side B B72 EBI_OE_b B73 EBI_D7 B74 EBI_D6 B75 EBI_D5 B76 EBI_D4 B77 EBI_D3 B78 EBI_D2 B79 EBI_D1 B80 EBI_D0 B81 GND B82 3.3V Table 6-2. TWR-P1025 Primary Connector Pinout Pin# Name GND D3 3 ...
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... Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# D16 GPIO18 D17 GPIO19 / SDHC_D4 D18 GPIO20 / SDHC_D5 D19 ETH_TXD1 D20 ETH_TXD0 D21 ULPI_NEXT / USB_HS_DM D22 ULPI_DIR / USB_HS_DP D23 UPLI_DATA5 / USB_HS_VBUS D24 ULPI_DATA6 / USB_HS_ID D25 ULPI_DATA7 D26 GND D27 LCD_HSYNC / LCD_P24 D28 LCD_VSYNC / LCD_P25 ...
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... Tower Elevator Connections Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# D35 GPIO21 D36 3.3V D37 PWM15 D38 PWM14 D39 PWM13 D40 PWM12 D41 CAN2_RX D42 CAN2_TX D43 LCD_CONTRAST D44 LCD_OE / LCD_P27 D45 LCD_D0 / LCD_P0 D46 LCD_D1 / LCD_P1 D47 LCD_D2 / LCD_P2 D48 LCD_D3 / LCD_P3 ...
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... Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# D56 IRQ_O / SPI2_CS3_b D57 IRQ_N D58 IRQ_M D59 IRQ_L D60 IRQ_K D61 IRQ_J D62 IRQ_I D63 LCD_D18 / LCD_P18 / SD_RX_0 D64 LCD_D19 / LCD_P19 / SD_RXb_0 D65 GND D66 EBI_AD20 / LCD_P42 / SD_GND D67 EBI_AD21 / LCD_P43 / SD_GND D68 ...
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... Tower Elevator Connections Table 6-2. TWR-P1025 Primary Connector Pinout (continued) Pin# D72 EBI_AD26 / LCD_P48 / SD_RX_2 D73 EBI_AD27 / LCD_P49 / SD_RXb_2 D74 EBI_AD28 / LCD_P50 / SD_GND D75 EBI_AD29 / LCD_P51 / SD_GND D76 EBI_AD30 / LCD_P52 / SD_RX_3 D77 EBI_AD31 / LCD_P53 / SD_RXb_3 D78 LCD_D20 / LCD_P20 / SD_GND D79 LCD_D21 / LCD_P21 / ...
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... Appendix A Revision History This appendix provides a list of the major differences between current TWR-P1025 hardware user guide and its previous revisions. A.1 Version Number 2 Updated section 1.5 QorIQ P1025 Device Notification. A.2 Version Number 1 Added section 1.5 QorIQ P1025 Device Notification. Updated Table 3.4 CPU Speed Selection. ...