DS4830EVKIT# Maxim Integrated, DS4830EVKIT# Datasheet - Page 7

• Manufacturer Part Number: DS4830EVKIT#
• Description: Development Boards & Kits - Other Processors DS4830 Eval Kit
• Manufacturer: Maxim Integrated

Specifications of DS4830EVKIT#

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: DS4830
• Interface Type: I2C
• Operating Supply Voltage: 3 V to 3.6 V
• Part # Aliases: 90-4830T#EVK

3-WIRE DIGITAL INTERFACE SPECIFICATION
(V
SPI DIGITAL INTERFACE SPECIFICATION
(V
Maxim Integrated
MCL Clock Frequency
MCL Duty Cycle
MDIO Setup Time
MDIO Hold Time
MCS Pulse-Width Low
MCS Leading Time Before the
First MCL Edge
MCS Trailing Time After the Last
MCL Edge
MDIO, MCL Load
SPI Master Operating Frequency
SPI Slave Operating Frequency
SPI I/O Rise/Fall Time
MSPICK Output Pulse-Width
High/Low
MSPIDO Output Hold After
MSPICK Sample Edge
MSPIDO Output Valid to MSPICK
Sample Edge (MSPIDO Setup)
MSPIDI Input Valid to MSPICK
Sample Edge (MSPIDI Setup)
MSPIDI Input to MSPICK Sample
Edge Rise/Fall Hold
MSPICK Inactive to MSPIDO
Inactive
SSPICK Input Pulse-Width High/
Low
SSPICS Active to First Shift Edge
SSPIDI Input to SSPICK Sample
Edge Rise/Fall Setup
SSPIDI Input from SSPICK
Sample Edge Transition Hold
SSPIDO Output Valid After
SSPICK Shift Edge Transition
DD
DD
= 3.0V to 3.6V, T
= 3.0V to 3.6V, T
PARAMETER
PARAMETER
A
A
= -40NC to +85NC, unless otherwise noted.) (See
= -40NC to +85NC, unless otherwise noted.) (See
t
t
1/t
MCH
SYMBOL
1/t
SCH
SYMBOL
t
f
SPI_RF
SCLOUT
t
t
MSPICK
t
t
SSPICK
t
C
t
t
MOH
MOV
t
t
MLH
t
3WDC
t
SOV
MIH
SSE
MIS
SIS
SIH
CSW
t
t
, t
, t
B3W
DH
DS
t
t
L
T
MCL
SCL
C
Total bus capacitance on one line
L
= 15pF, pullup = 560I
CONDITIONS
CONDITIONS
Optical Microcontroller
Figure
Figure 3
2.)
and
Figure
t
t
t
t
MSPICK
MSPICK
MSPICK
MSPICK
- t
- t
- t
2t
- t
t
t
t
SPI_RF
SPI_RF
SPI_RF
4.)
SPI_RF
SPI_RF
SPI_RF
SPI_RF
SPI_RF
MIN
0
MIN
100
100
500
500
500
/2
/2
/2
/2
t
SCL
TYP
TYP
833
50
/2
DS4830
2t
f
f
MAX
SYS
SYS
SPI_RF
MAX
25
10
/2
/4
UNITS
UNITS
MHz
MHz
kHz
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
7