IS61LV256AL-10TLI-TR ISSI, Integrated Silicon Solution Inc, IS61LV256AL-10TLI-TR Datasheet - Page 7

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IS61LV256AL-10TLI-TR

Manufacturer Part Number
IS61LV256AL-10TLI-TR
Description
IC SRAM 256KBIT 10NS 28TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61LV256AL-10TLI-TR

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
256K (32K x 8)
Speed
10ns
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
28-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AC WAVEFORMS
WRITE CYCLE NO. 1
IS61LV256AL
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
07/29/09
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1.
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or
falling edge of the signal that terminates the Write.
wc
sce
aw
ha
sa
Pwe
Pwe
sd
hd
hzwe
lzwe
ADDRESS
1
2
(3)
(3)
D
OUT
WE
D
CE
IN
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold
from Write End
Address Setup Time
WE Pulse Width (OE HIGH)
WE Pulse Width (OE LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
DATA UNDEFINED
t
(CE Controlled, OE is HIGH or LOW)
SA
t
HZWE
t
VALID ADDRESS
AW
t
t
PWE1
PWE2
t
t
Min.
SCE
6.5
WC
10
10
8
8
0
0
7
0
0
-10 ns
HIGH-Z
(1,2)
Max.
3.5
(1 )
t
(Over Operating Range)
SD
DATA
IN
VALID
Min. Max.
12
12
8
8
0
0
8
7
0
0
-12 ns
t
HD
t
LZWE
5
t
HA
CE_WR1.eps
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7

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