ATRF4CE-EK Atmel, ATRF4CE-EK Datasheet - Page 23

• Manufacturer Part Number: ATRF4CE-EK
• Description: Development Boards & Kits - Wireless RF4CE evaluation kit
• Manufacturer: Atmel

Specifications of ATRF4CE-EK

• Rohs: yes
• Product: Evaluation Kits
• Tool Is For Evaluation Of: ATmega128RFA1
• Core: AVR
• Frequency: 2.4 GHz
• Operating Supply Voltage: 3 V
• Description/function: Kit contains two radio controller boards assembled with the ATmega128RFA1 and a SMA connector at the RF port
• Factory Pack Quantity: 1

Wafer Level Reliability
WLR involves the reliability evaluation of new technologies during development and an ongoing monitor of these
technologies on wafers to provide the earliest possible feedback. Special test structures have been developed for various
technologies to evaluate the fundamental reliability of design rules and technologies. Wafer Level Test structures are
designed to assess the reliability of the materials and fabrication processes such as thin oxides, metalization and dielectric
structures, and the basic transistor ruggedness. Structures are designed for the following tests:
Appropriate structures are identified for new technologies and used to evaluate the robustness and reliability.
Most structures are used to monitor reliability and process performance on an ongoing basis. These structures are also
used to perform the initial assessment of major improvement changes.
Reliability Qualification Methodology
Wafer Level Reliability Tests, though very comprehensive and useful, have not achieved universal acceptance to replace
reliability tests performed on the finished product due to the less known interactions between die, package, and assembly
processes. For this reason, Atmel maintains a stringent reliability qualification methodology for new products, technologies,
and packages on packaged product according to established standards of JEDEC (JESD47), AEC (AEC-Q100)
and MIL (MIL-STD-883).
These reliability tests are designed to accelerate potential failure mechanisms due to process technology, package
and die interaction, and worst-case environmental conditions. Each test and its purpose are described below.
Data Retention Bake (DRB)
This test is used to measure a device’s ability to retain a charge for extended periods of time without applying
voltage bias. Stressing at high temperatures (150°C for plastic packages) accelerates any discharge causing the memory
state to change.
Electrostatic Discharge (ESD)
This test is conducted in order to evaluate a device’s Sensitivity to ESD charges. Human Body (HBM) and Charged
Device (CDM) models are used to replicate the handling environment.
Endurance Test (END)
This test is performed in order to evaluate a device’s ability to be programmed, erased, and verified repeatedly
for a pre-determined number of cycles. This test is used for products that are used in applications requiring multiple
programming and erase cycles.
Atmel Quality Handbook
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Gate Oxide Integrity (GOI)
Time Dependent Dielectric Breakdown (TDDB)
Gate Oxide Charge Retention (Qbd)
Hot Carrier Injection (HCI)
Negative Bias Temperature Instability (NBTI)
Metal and Plug Step Coverage
Metal Electromigration (EM)
Ionic Contamination
Interlayer Dielectric Integrity
Transistor Latch Up
Transistor Performance and Ruggedness
Process Induced Charging
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