MAX1320EVB16 Maxim Integrated, MAX1320EVB16 Datasheet - Page 17
MAX1320EVB16
Manufacturer Part Number
MAX1320EVB16
Description
Data Conversion IC Development Tools 8-/4-/2-Channel 14-Bit Simultaneous-Sampling ADCs with 10V 5V and 0 to +5V Analog Input Ranges
Manufacturer
Maxim Integrated
Series
MAX1316, MAX1317, MAX1318, MAX1320, MAX1321, MAX1322, MAX1324, MAX1325, MAX1326r
Datasheet
1.MAX1324ECMC1W.pdf
(27 pages)
Specifications of MAX1320EVB16
Interface Type
Parallel
The data throughput (f
MAX1320–MAX1322/MAX1324–MAX1326 is a function
of the clock speed (f
10MHz. In external-clock mode, 100kHz ≤ f
12.5MHz. When reading during conversion (Figures 5
and 6), calculate f
where N is the number of active channels and t
includes acquistion time t
inactivity before the rising edge of CONVST. Typically use
t
output bus from corrupting signal acquistion. See the
Starting a Conversion section for more information.
Table 3. Throughput vs. Channels Sampled (t
Figure 5. Read During Conversion—Two Channels Selected, Internal Clock
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
QUIET
CHANNELS
SAMPLED
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
CONVST
(N)
D0–D13
1
2
3
4
5
6
7
8
= t
f
EOC
TH
RD
ACQ
=
+ 50ns, and prevent disturbance on the
t
QUIET
TH
TRACK
CLOCK CYCLES
______________________________________________________________________________________
t
UNTIL LAST
1
CLK
as follows:
RESULT
+
TH
SAMPLE
). In internal-clock mode, f
16
19
22
25
28
31
34
37
ACQ
16
) of the MAX1316–MAX1318/
. t
+
1
QUIET
3
f
Data Throughput
x N
CLK
(
is the period of bus
CLOCK CYCLE FOR
−
READING LAST
1
CONVERSION
)
t
CONV
+
1
1
1
1
1
1
1
1
1
CLK
CLK
QUIET
=
≤
t
20
t
10
QUIET
CONVERSION
Figures 5 and 6 show the interface signals for initiating a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more chan-
nels are selected, the results are available successively
every third clock cycle. CS can be low at all times; it can
be low during the RD cycles, or it can be the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC to go low (about 1.6µs in internal-clock
mode or 17 clock cycles in external-clock mode) before
reading the first conversion result. Read the conversion
result by bringing RD low, thus latching the data to the
parallel digital-output bus. Bring RD high to release the
digital bus. Wait for the next falling edge of EOC (about
300ns in internal-clock mode or three clock cycles in
external-clock mode) before reading the next result.
When the last result is available, EOLC goes low.
HOLD
TIME (ns)
t
13
t
CH0
12
TOTAL
1900
2200
2500
2800
3100
3400
3700
4000
= t
t
11
t
NEXT
ACQ
= 200ns, f
Reading a Conversion Result
SAMPLES PER
t
3
SECOND
(ksps)
1200
1429
1613
1765
1892
2000
Reading During a Conversion
526
909
CH1
CLK
= 10MHz)
PER CHANNEL
THROUGHPUT
TRACK
(ksps)
526
455
400
357
323
294
270
250
17