DK-START-5AGXB3N Altera Corporation, DK-START-5AGXB3N Datasheet - Page 2

• Manufacturer Part Number: DK-START-5AGXB3N
• Description: Programmable Logic IC Development Tools FPGA Development Kit For 5AGXFB3H4F35C5N
• Manufacturer: Altera Corporation
• Type: FPGAr

Specifications of DK-START-5AGXB3N

• Rohs: yes
• Product: Starter Kits
• Tool Is For Evaluation Of: Arria V
• Description/function: Altera Arria V starter kit
• For Use With: Arria V

Figure 1: Arria V GX Starter Board with a 5AGXB3ES FPGA Device
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HSMC
SMA
Dedicated clock domain from Si 5338 clock generator for xcvr refclk
DDR3 SDRAM x32
SSRAM
User IO
Configuration
JTAG header
Embedded USB Blaster II
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Up to 2.97 Gbps
Uses National Semiconductor driver/receiver LMH0384SQ/LMH0303SQx
Requires 148.5 MHz and 148.35 MHz at XCVR refclk to support US and EU standard respectively
Use VCXO to fine tune and lock to the recovered CDR frequency
Requires 125 MHz CLKIN for core logic
x8 XCVR up to 6.375 Gbps
Not complied to PCI Express
x4 CMOS
x17 differential using dedicated TX/RX channel
x2 low-voltage differential signalling (LVDS) clock in
x2 differential clock out
I2C
JTAG
Minimum current support
2A @ 3.3V
1A @ 12V
Dedicated clock domain from Si 5338 clock generator for xcvr refclk
HSMC loopback with BTS GUI
7x XCVR TX/RX channel
1x LVDS clock input
Micron MT41J64M16JT-15E DDR3 SDRAM 8MX16X8
Two devices: 2 x16 width = x32
BTS DDR3 SDRAM GUI using Uniphy and high performance (HP) controller II
1024k x18, 18 Mb ISSI IS61VPS102418A
Shared address or data with flash
LCD character
x4 DIP switch
x3 PB
x4 LED
FPP x16 mode
Dual flash 512Mbit Numonyx PC28F512P30BF (52 MHz F
Cypress Microcontroller CY7C68013A as USB PHY 2.0
MAX II
Ethernet
10/100/1000 Base-T
RJ-45 connector, on-board LED for link status
Marvell Ethernet PHY 88E1111
Requires 100 MHz and 125 MHz clock from CLKIN
®
(PCIe
®
) HIP pin assignment
MAX
)
7/6/2012