KITMMA9550LEVM Freescale Semiconductor, KITMMA9550LEVM Datasheet - Page 12

• Manufacturer Part Number: KITMMA9550LEVM
• Description: Acceleration Sensor Development Tools EVM KIT FOR MMA9550L
• Manufacturer: Freescale Semiconductor

Specifications of KITMMA9550LEVM

• Rohs: yes
• Tool Is For Evaluation Of: MMA955xL
• Acceleration: 2 g, 4 g, 8 g
• Sensing Axis: Triple Axis
• Interface Type: I2C, SPI
• Operating Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Current: 3.1 mA
• Output Type: Analog, Digital

MMA955xL
12
3.3
This section provides a brief description of the various pin functions available on the MMA955xL platform. Ten of the device pins
are multiplexed with Rapid GPIO (RGPIO) functions. The “Pin Function #1” column in
active when the hardware exits the reset state. Freescale or user firmware can use the pin mux-control registers in the System
Integration Module (SIM) to change pin assignments for each pin after reset. For detailed information about these registers, see
the MMA955xL Three-Axis Accelerometer Reference Manual (MMA955xLRM).
V
V
remove any digital noise that can be present on the 1.8V supply. (See
RESETB: The RESETB pin is an open-drain, bidirectional pin with an internal, weak, pullup resistor. At start up, it is configured
as an input pin, but also can be programmed to become bidirectional. Using this feature, the MMA955xL device can reset external
devices for any purpose other than power-on reset. Reset must be pulled high at startup. After startup, Reset may be asserted
to reset the device. The total external capacitance to ground has to be limited when using RESETB-pin, output-drive capability.
For more details, see the “System Integration Module” chapter of the MMA955xL Three-Axis Accelerometer Reference Manual
(MMA955xLRM).
Slave I
controlled via the serial port or via the slave SPI interface.
Master I
Analog-to-Digital Conversion: AN0, AN1: The on-chip ADC can be used to perform a differential, analog-to-digital conversion
based on the voltage present across pins AN0(-) and AN1(+). Conversions for these pins are at the same Output Data Rate
(ODR) as the MEMS transducer signals. Input levels are limited to 1.8V differential.
Rapid General Purpose I/O: RGPIO[9:0]: The ColdFire V1 CPU has a feature called Rapid GPIO (RGPIO). This is a 16-bit,
input/output port with single-cycle write, set, clear, and toggle functions available to the CPU. The MMA955xL device brings out
the lower 10 bits of that port as pins of the device.
Interrupts: INT: This input pin can be used to wake the CPU from a deep-sleep mode. It can be programmed to trigger on either
rising or falling edge, or high or low level. This pin operates as a Level-7 (high-priority) interrupt.
Debug/Mode Control: BKGD/MS: At start up, this pin operates as mode select. If this pin is pulled high during start up, the CPU
will boot normally and run code. If this pin is pulled low during start up, the CPU will boot into active Background-Debug Mode
(BDM). In BDM, this pin operates as a bidirectional, single-wire, background-debug port. It can be used by development tools for
downloading code into on-chip RAM and flash and to debug that code.
Timer: PDB_A and PDB_B: These are the two outputs of the programmable delay block.
Slave SPI Interface: SCLK, SDI, SDO and SSB: These pins control the slave SPI clock, data in, data out, and slave-select
signals, respectively. The MMA955xL platform can be controlled via this serial port or via the slave-I
cial function at startup that selects the Slave interface mode. Low at startup selects SPI and high selects I
INT_O: The slave-port output interrupt pin. This pin can be used to flag the host when a response to a command is available to
read on the slave port.
TPMCH0 and TPMCH1: The I/O pin associated with 16-bit, TPM channel 0 and 1.
3.4
3.4.1
An internal circuit powered by V
ognized, it is important that V
must not be allowed to exceed the value specified in
3.4.2
•
•
•
•
DD
DDA
Provide a low-impedance path from the board power supply to each power pin (V
board ground to each ground pin (V
Place 0.01 to 0.1-µF capacitors as close as possible to the package supply pins to meet he minimum bypass requirement.
The recommended bypass configuration is to place one bypass capacitor on each of the V
and tantalum capacitors tend to provide better tolerances.
Ensure that capacitor leads and associated printed-circuit traces that connect to the chip V
short as possible.
Bypass the power and ground with a capacitor of approximately 1 µF and a number of 0.1-µF ceramic capacitors.
and V
and V
2
C port: SDA0 and SCL0: These are the slave-I
2
C: SDA1 and SCL1: These are the master-I
SS
Pin Function Descriptions
System Connections
Power Sequencing
Layout Recommendations
SSA
: Digital power and ground. V
: Analog power and ground. V
DD
is powered up before or simultaneously with V
DDA
provides the device with a power-on-reset signal. In order for this signal to be properly rec-
SS
and V
DD
is nominally 1.8V.
DDA
SSA
is nominally 1.8V. To optimize performance, the V
).
Table 7 on page
2
C clock and data signals, respectively.
2
C data and clock signals, respectively. The MMA955xL device can be
17.
Figure 5
DDA
and
. The voltage potential between V
Figure 6 on page
DD
Table 3 on page 11
and V
DD
DDA
DD
/V
Freescale Semiconductor, Inc.
SS
and V
) on the device and from the
2
C interface. SBB has a spe-
DDA
pairs. V
17.)
SS
line can be filtered to
lists which function is
2
C.
(GND) pins are as
DDA
/V
DD
SSA
and V
. ceramic
Sensors
DDA