IS42S32200E-7TL-TR ISSI, Integrated Silicon Solution Inc, IS42S32200E-7TL-TR Datasheet - Page 14

• Manufacturer Part Number: IS42S32200E-7TL-TR
• Description: IC SDRAM 64MBIT 143MHZ 86TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S32200E-7TL-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 86-TSOPII
• Organization: 2Mx32
• Density: 64Mb
• Address Bus: 13b
• Access Time (max): 8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S32200E
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS\ latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information
MODE REGISTER DEFINITION
14
BA0,1
0
(1)
A10/AP
Write Burst Mode
M9
0
1
0
(1)
Mode
Burst Write
Single-Bit Write
A9
A8
MRS
M8 M7
—
0
A7
—
0
Integrated Silicon Solution, Inc. — www.issi.com —
MRS
Mode Register Set
All Other States Reserved
A6
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Note:
1. Maintain low during Mode Register Set.
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 and M12 are reserved for future use.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.
A4
Burst Type
M3 Type
CAS Latency
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Interleaved
Sequential
Burst Length
A3
2
3
M2 M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
A2
0
1
0
1
0
1
0
1
A1
Sequential
Reserved
Reserved
Reserved
Full Page
1
2
4
8
A0
Address Bus
Interleave
Reserved
Reserved
Reserved
Reserved
1
2
4
8
1-800-379-4774
Rev. 00D
06/02/08