MAX34561EVKIT# Maxim Integrated, MAX34561EVKIT# Datasheet - Page 7
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MAX34561EVKIT#
Manufacturer Part Number
MAX34561EVKIT#
Description
Power Management IC Development Tools 12V&5V DUAL E-FUSE
Manufacturer
Maxim Integrated
Series
MAX34561r
Datasheet
1.MAX34561EVKIT.pdf
(11 pages)
Specifications of MAX34561EVKIT#
Rohs
yes
Part # Aliases
90-34561#EVK
The MAX34561 has hot-plug controls for both +12V and
+5V power rails. The circuitry for the +12V and +5V con-
trols are independent of each other and can be treated
as two separate hot-plug switches, even though the GND
pin is common between the two switches. The sections
that follow are written from the +12V circuit perspective,
but also apply for the +5V switch control.
The device begins to operate when the supply voltage
V
V
circuit and TIMER12 (TIMER5) become active. Once the
device has been enabled, a gate voltage is applied to
the corresponding power MOSFET, allowing current to
begin flowing from V
The speed of the output-voltage ramp is controlled by
the capacitance placed at the VRAMP12 (VRAMP5) pin.
The load current is continuously monitored during the
initial conduction (I
responding MOSFET is fully on (I
current exceeds the current limit that is set by the exter-
nal resistance at ILIM12 (ILIM5), the gate voltage of the
corresponding power MOSFET is decreased, reducing
the output current to the set current limit.
Current is limited by the device comparing the volt-
age difference between LOAD12 (LOAD5) and ILIM12
(ILIM5) to an internal reference voltage. If the output cur-
rent exceeds the limit that is set by the R
resistor, the gate voltage of the corresponding power
MOSFET is decreased, which reduces the output current
to the load.
CC12
UR12
PIN
22
23
24
—
(or V
(or V
UR5
CC5
). At this level, the corresponding enable
VRAMP5
) exceeds its undervoltage lockout level,
TIMER5
NAME
ARD5
EP
SCL12
CC12
Detailed Description
or I
(V
5V Autoretry Disable. Connect this pin to GND to disable automatic retry functionality; the device
latches off during an overtemperature fault. Leave this pin open to enable automatic retry function.
This pin contains a pullup (R
side is not used, connect this pin to GND.
5V Voltage Ramp Control. A capacitor connected to this pin determines the voltage ramp of the
LOAD5 output during turn-on according to the equation: dV
5V Enable Delay Control. A capacitor connected to this pin determines the enable delay according
to the equation: Enable Delay = C
Exposed Pad. Connect to ground. The EP must be soldered to ground for proper thermal and elec-
trical operation.
CC5
SCL5
) to LOAD12 (LOAD5).
OVL12
) and after the cor-
or I
ILIM12
OVL5
(R
). If the
ILIM5
PU5
)
) to V
TIMER5
12V/5V Hot-Plug Switch
CC5
When the output power is initially ramping up, the current
limit is I
is fully on, the current limit is I
(I
short on initial power-up.
The device acts as a fuse and automatically disables the
current flowing to the load when the temperature of the
power corresponding MOSFET has exceeded the shut-
down junction temperature, T
The voltage level of TIMER12 (TIMER5) is compared to
an internal source (see the Functional Diagram). When
the level on the pin exceeds V
puts a low level. This then turns on the voltage ramp
circuit, enabling the device’s output. TIMER12 (TIMER5)
can be configured into one of four different modes of
operation as listed in Table 1. TIMER12 (TIMER5) pin
was designed to work with most logic families. TIMER12
(TIMER5) has at least 250mV of hysteresis between V
and V
to drive TIMER12 (TIMER5) be tested to ensure proper
operation.
Table_1._TIMER__Pin_Modes
SCL5
Delayed Automatic Enable
Enable with Delay/Disable
. This pin is only sampled on device power-on. If the 5V
x (V
OPERATION_MODE
FUNCTION
Automatic Enable
OFF
) current limit protects the source if there is a dead
REF5
Enable/Disable
SCL12
. It is recommended that any logic gate used
/I
TIMER
Pin Description (continued)
(I
SCL5
).
LOAD5
). Once the corresponding MOSFET
= 2.3332 x (I
No connection to TIMER12
(TIMER5)
Capacitor C
to TIMER12 (TIMER5)
Open-collector device
Open-collector device and
C
SHDN
TIMER
OVL12
ON
TIMER_PIN_SETUP
, the comparator out-
.
_
(I
VRAMP
OVL5
TIMER_
Enable/Timer
/C
). The I
VRAMP5
connected
SCL12
).
ON
7