DS2726K Maxim Integrated, DS2726K Datasheet - Page 3

• Manufacturer Part Number: DS2726K
• Description: Power Management IC Development Tools
• Manufacturer: Maxim Integrated
• Series: DS2726r

Table 2
Cell balancing voltage:
Example:
Cell balancing will begin when a cell’s voltage is greater than 4.1V and will terminate when all cells’ voltages are
greater than 4.1V.
Number of Cells
The number of cells in the battery pack is set at the SEL0 and SEL1 pins through resistors R12, R13, R27, and
R28. R12 and R13 will pull SEL0 and SEL1 to VCC. R27 and R28 will pull CBS0 and CBS1 to VSS. V
by floating the pin. See Figure 2 for proper connections to stacks with fewer than 10 cells.
Table 3
Discharge Overcurrent
The RDOC pin is a 1μA current sink. The R34 resistor sets the discharge overcurrent voltage threshold.
The voltage seen at RDOC is sent to a comparator with the voltage seen at SNS. When V
will turn off. The voltage drop from Bat+ to the SNS pin is determined by the R
the FET section below for a description of R
Short Circuit Overcurrent
The RSC pin is a 1μA current sink. The R35 resistor sets the short circuit voltage threshold.
The voltage seen at RSC is sent to a comparator with the voltage seen at SNS. When V
turn off. The voltage drop from Bat+ to the SNS pin is determined by the R
FET section for a description of R
Discharge Overcurrent Delay
The short circuit delay time is set using the capacitor C14 connected to the CDOCD pin. The short circuit delay
time is defined by the equation:
Short Circuit Overcurrent Delay
The short circuit delay time is set using the capacitor C15 connected to the CSCD pin. The short circuit delay time
is defined by the equation:
FET
The FETs used on the DS2726 EV board are Vishay SUM110P06-07L. Refer to the data sheet for details.
The R
equivalent resistance is around 2.75m. Multiply R
the desired SC current to get V
DS_ON
rating of this FET is typ 5.5m at V
CBS0
CBS1
SEL0
SEL1
SC
.
DS_ON
0.00
V
V
V
V
IL
IL
5
IL
IL
and a reference to the data sheet of the FET used the on EV board.
Cell Balancing Threshold Offset from VOV (V)
0.05
V
V
OVS0, OVS1, CBS0, and CBS1 = V
V
V
IM
IL
DS_ON
6
IM
IL
t
Number of Series Connected Cells
DOCD
GS
t
SCD
0.10
R34 x 1μA = V
V
V
V
R35 x 1μA = V
and a link to the datasheet of the FET used the on EV board.
V
V
= -10V. The EV kit board has two FETs in parallel, therefore, the
OV
IH
7
IL
IH
IL
DS_ON
= C
= C
4.5V - 0.4V = 4.1V
- V
3 of 5
0.15
SCD
DOCD
V
V
CBTO
V
V
8
IM
times the desired DOC to get V
IL
IM
IL
x 500k
x 32M
= V
0.20
V
V
V
V
DOC
9
SC
IM
IM
CB
IM
IM
0.25
V
V
10
V
V
IH
IM
IM
IH
DS_ON
0.30
V
V
10
V
V
IH
IL
IL
IH
DS_ON
IH
resistance of the DC FET. See the
V
V
10
0.35
V
V
IM
IH
resistance of the DC FET. See
IM
IH
RSC
V
V
10
DOC
0.40
V
V
IH
IH
RDOC
IH
IH
> V
. Multiply R
SNS
> V
the DC FET will
SNS
IM
the DC FET
is achieved
DS_ON
times