IS42S32160B-75TL-TR ISSI, Integrated Silicon Solution Inc, IS42S32160B-75TL-TR Datasheet - Page 14
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IS42S32160B-75TL-TR
Manufacturer Part Number
IS42S32160B-75TL-TR
Description
IC SDRAM 512MBIT 133MHZ 86TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS42S32160B-75TL-TR.pdf
(62 pages)
Specifications of IS42S32160B-75TL-TR
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (16M x 32)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
86-TSOPII
Organization
16Mx32
Density
512Mb
Address Bus
15b
Access Time (max)
5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
125mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
IS42S32160B
14
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank
WRITE with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n
n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE
to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE
to bank m.
when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after
t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will
be data-in registered one clock prior to the READ to bank m.
Internal
States
Internal
States
NOTE: 1. DQM is LOW.
NOTE: 1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
WRITE With Auto Precharge Interrupted by a READ
COMMAND
ADDRESS
COMMAND
BANK m
BANK n
ADDRESS
BANK m
BANK n
CLK
DQ
Page Active
NOP
T0
Page Active
T0
NOP
WRITE - AP
BANK n,
Page Active
BANK n
COL a
T1
D
WRITE - AP
a
IN
BANK n,
WRITE with Burst of 4
Page Active
BANK n
COL a
T1
D
a
IN
WRITE with Burst of 4
T2
a + 1
D
NOP
IN
T2
a + 1
D
NOP
IN
a + 2
T3
D
IN
BANK m,
READ - AP
T3
COL d
BANK m
Interrupt Burst, Write-Back
t
WR - BANK n
CAS Latency = 3 (BANK m)
READ with Burst of 4
BANK m,
WRITE - AP
COL d
BANK m
T4
D
Interrupt Burst, Write-Back
t
d
IN
WR - BANK n
T4
WRITE with Burst of 4
Integrated Silicon Solution, Inc. — www.issi.com
NOP
T5
d + 1
NOP
D
T5
IN
NOP
Precharge
t
RP - BANK n
T6
d + 2
NOP
Precharge
D
t RP - BANK n
IN
T6
D
NOP
OUT
d
DON’T CARE
DON’T CARE
T7
d + 3
NOP
D
t WR - BANK m
IN
Write-Back
T7
D
d + 1
NOP
t RP - BANK m
OUT
I
®
Rev. 00C
03/27/08