M25P20-VMP6G NUMONYX, M25P20-VMP6G Datasheet - Page 23

• Manufacturer Part Number: M25P20-VMP6G
• Description: IC FLASH 2MBIT 50MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P20-VMP6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: VDFPN
• No. Of Pins: 8
• Base Number: 25
• Frequency: 50MHz
• Ic Generic Number: 25P20
• Memory Configuration: 256K X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Signal
W
1
0
1
0
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
SRWD
Bit
0
0
1
1
Protection Modes
Protected
Hardware
Protected
Software
(HPM)
(SPM)
Mode
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP1 and BP0 bits can be
changed
Status Register is
Hardware write protected
The values in the SRWD,
BP1 and BP0 bits cannot
be changed
Write Protection of the
Status Register
Protected against
Page Program,
Sector Erase and
Bulk Erase
Protected against
Page Program,
Sector Erase and
Bulk Erase
Protected Area
Table
7.
Memory Content
(1)
Ready to accept
Page Program and
Sector Erase
instructions
Ready to accept
Page Program and
Sector Erase
instructions
Unprotected
Area
Table
(1)
2.
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