M25PX80-VMN6TP NUMONYX, M25PX80-VMN6TP Datasheet - Page 37

• Manufacturer Part Number: M25PX80-VMN6TP
• Description: IC FLASH 8MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PX80-VMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PX80-VMN6TPTR

6.14
Figure 20. How to permanently lock the 64 OTP bytes
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the
targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is
shown in
has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not
executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than t
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 21. Write to Lock Register (WRLR) instruction sequence
S
C
DQ0
Byte
0
Byte
1
Figure
Byte
2
0
1
21. Chip Select (S) must be driven High after the eighth bit of the data byte
2
Instruction
3
4
5
6
7
64 data bytes
MSB
23
8
Bit 4 to bit 7 are NOT
22 21
X
9 10
24-Bit Address
programmable
X
X
3
28 29 30 31 32 33 34 35
2
X
1
bit 3 bit 2 bit 1 bit 0
0
MSB
7
SHSL
6
Lock Register
5
minimum value.
4
OTP Control byte
In
When bits 3, 2, 1, and 0 = 0,
the 64 OTP bytes become
READ only
Byte
63
3
36 37 38
ai13587
2
Byte
64
1
0
39
AI13740
37/60