M29W800DT70N6F NUMONYX, M29W800DT70N6F Datasheet - Page 23
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M29W800DT70N6F
Manufacturer Part Number
M29W800DT70N6F
Description
IC FLASH 8MBIT 70NS 48TSOP
Manufacturer
NUMONYX
Series
Axcell™r
Datasheet
1.M29W800DB70ZE6F.pdf
(52 pages)
Specifications of M29W800DT70N6F
Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
8M (1M x 8 or 512K x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Cell Type
NOR
Density
8Mb
Access Time (max)
70ns
Interface Type
Parallel
Boot Type
Top
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
10mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
5
5.1
5.2
Status register
Bus read operations from any address always read the status register during program and
erase operations. It is also read during erase suspend when an address within a block being
erased is accessed.
The bits in the status register are summarized in
Data polling bit (DQ7)
The data polling bit can be used to identify whether the program/erase controller has
successfully completed its operation or if it has responded to an erase suspend. The data
polling bit is output on DQ7 when the status register is read.
During program operations the data polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the program operation the memory
returns to read mode and bus read operations from the address just programmed output
DQ7, not its complement.
During erase operations the data polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the erase operation the memory returns to read
mode.
In erase suspend mode the data polling bit will output a ’1’ during a bus read operation
within a block being erased. The data polling bit will change from a ’0’ to a ’1’ when the
program/erase controller has suspended the erase operation.
Figure 7: Data polling flowchart
address is the address being programmed or an address within the block being erased.
Toggle bit (DQ6)
The toggle bit can be used to identify whether the program/erase controller has successfully
completed its operation or if it has responded to an erase suspend. The toggle bit is output
on DQ6 when the status register is read.
During program and erase operations the toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive bus read operations at any address. After successful completion of the
operation the memory returns to read mode.
During erase suspend mode the toggle bit will output when addressing a cell within a block
being erased. The toggle bit will stop toggling when the program/erase controller has
suspended the erase operation.
If any attempt is made to erase a protected block, the operation is aborted, no error is
signalled and DQ6 toggles for approximately 100 μs. If any attempt is made to program a
protected block or a suspended block, the operation is aborted, no error is signalled and
DQ6 toggles for approximately 1 μs.
Figure 8: Data toggle flowchart
gives an example of how to use the toggle bit.
gives an example of how to use the data polling bit. A valid
Table 7: Status register
bits.
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