M25P128-VMF6TPB NUMONYX, M25P128-VMF6TPB Datasheet - Page 22

• Manufacturer Part Number: M25P128-VMF6TPB
• Description: IC FLASH 128MBIT 65NM 3V SO16
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P128-VMF6TPB

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: SO-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
6.4.1
6.4.2
6.4.3
6.4.4
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Read status register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in
Table 6.
The status and control bits of the Status Register are as follows:
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/V
(W/V
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/V
this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become
Status Register Write Protect
SRWD
PP
b7
) signal allow the device to be put in the Hardware Protected mode (when the Status
Status register format
PP
) signal. The Status Register Write Disable (SRWD) bit and Write Protect
0
0
BP2
BP1
Block Protect Bits
Write Enable Latch Bit
BP0
Table
Figure
PP
) is driven Low). In
Write In Progress Bit
WEL
2) becomes
11.
WIP
b0