PSD834F2-70M STMicroelectronics, PSD834F2-70M Datasheet - Page 91

• Manufacturer Part Number: PSD834F2-70M
• Description: IC FLASH 2MBIT 70NS 52QFP
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-70M

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2005

Table 57. WRITE Timing (5V devices)
Note: 1. Any input used to select an internal PSD function.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
LVLX
AVLX
LXAX
AVWL
SLWL
DVWH
WHDX
WLWH
WHAX1
WHAX2
WHPV
DVMV
AVPV
WLMV
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
Data Valid to Port Output Valid
Using Macrocell Register
Preset/Clear
Address Input Valid to Address
Output Delay
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
Parameter
Doc ID 10552 Rev 3
Conditions
(Notes
(Notes
(Notes
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
(Note
3,6
1,3
3,5
3,4
1
1
3
3
3
3
3
3
2
)
)
)
)
)
)
)
)
)
)
)
)
)
Min Max Min Max Min Max
15
12
25
31
4
7
8
4
6
0
-70
27
42
20
48
PSD813F2V, PSD854F2V
20
15
15
35
35
6
8
5
8
0
-90
30
55
25
55
28
10
11
20
20
45
45
10
5
0
-15
38
65
30
65
91/109
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns