CAT93C46YI-GT3 ON Semiconductor, CAT93C46YI-GT3 Datasheet - Page 6

• Manufacturer Part Number: CAT93C46YI-GT3
• Description: IC EEPROM 1KBIT 2MHZ 8TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT93C46YI-GT3

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8 or 64 x 16)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t
self clocking for auto−clear and data store cycles on the
memory location specified in the instruction. The clocking
of the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C46
can be determined by selecting the device and polling the
DO pin. Since this device features Auto−Clear before write,
it is NOT necessary to erase a memory location before it is
written into.
Erase
(Chip Select) pin must be de−asserted for a minimum of
t
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
CSMIN
DO
SK
CS
DI
After receiving a WRITE command (Figure 5), address
Upon receiving an ERASE command and address, the CS
(Figure 6). The falling edge of CS will start the self
CSMIN
1
0
. The falling edge of CS will start the
1
A
N
A
N−1
Figure 5. Write Instruction Timing
HIGH−Z
http://onsemi.com
A
0
6
D
N
Erase All
(Chip Select) pin must be deselected for a minimum of
t
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device and
polling the DO pin. Once cleared, the contents of all memory
bits return to a logical “1” state.
Write All
(Chip Select) pin must be deselected for a minimum of
t
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C46 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
CSMIN
CSMIN
Upon receiving an ERAL command (Figure 7), the CS
Upon receiving a WRAL command and data, the CS
. The falling edge of CS will start the self clocking
(Figure 8). The falling edge of CS will start the self
D
0
t
SV
t
t
CSMIN
EW
STATUS
VERIFY
BUSY
READY
HIGH−Z
STANDBY
t
HZ