CAT25128LI-G ON Semiconductor, CAT25128LI-G Datasheet - Page 7

• Manufacturer Part Number: CAT25128LI-G
• Description: IC EEPROM 128KBIT 10MHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT25128LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Density: 128Kb
• Interface Type: Serial (SPI)
• Organization: 16Kx8
• Access Time (max): 75ns
• Frequency (max): 5MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temp Range: -40C to 85C
• Supply Current: 4mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Maximum Clock Frequency: 10 MHz
• Access Time: 75 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 25128LI-G

Byte Write
sequence, by sending a WRITE instruction, a 16−bit address
and data as shown in Figure 5. Only 14 significant address
bits are used by the CAT25128. The rest are don’t care bits,
as shown in Table 11. Internal programming will start after
the low to high CS transition. During an internal write cycle,
all commands, except for RDSR (Read Status Register) will
be ignored. The RDY bit will indicate if the internal write
cycle is in progress (RDY high), or the device is ready to
accept commands (RDY low).
Table 11. BYTE ADDRESS
CAT25128
Once the WEL bit is set, the user may execute a write
SCK
SCK
SO
CS
SO
CS
SI
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
Device
0
0
0
0
0
0
1
1
0
0
2
HIGH IMPEDANCE
2
0
0
3
3
OPCODE
OPCODE
0
0
4
4
Address Significant Bits
0
0
5
5
1
1
6
A13 − A0
6
0
0
Figure 6. Page WRITE Timing
Figure 5. Byte WRITE Timing
7
7
A
A
N
N
8
8
BYTE ADDRESS*
BYTE ADDRESS*
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HIGH IMPEDANCE
21 22 23 24 25 26 27
21 22 23 24−31 32−39
7
Page Write
may continue sending data, up to a total of 64 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Following completion of the write cycle, the CAT25128 is
automatically returned to the write disable state.
Address Don’t Care Bits
A
A
After sending the first data byte to the CAT25128, the host
0
0
Byte 1
D7 D6 D5 D4 D3 D2 D1 D0
Data
A15 − A14
* Please check the Byte Address Table (Table 11)
* Please check the Byte Address Table (Table 11)
Byte 2
Data
DATA IN
Byte 3
DATA IN
Data
24+(N−1)x8−1 .. 24+(N−1)x8
28
Data Byte N
7..1
29 30 31
# Address Clock Pulses
0
24+Nx8−1
16