DS28EC20P+ Maxim Integrated Products, DS28EC20P+ Datasheet
DS28EC20P+
Specifications of DS28EC20P+
Related parts for DS28EC20P+
DS28EC20P+ Summary of contents
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... PCB Identification Wireless Base Stations ORDERING INFORMATION PART TEMP RANGE DS28EC20+ -40°C to +85°C DS28EC20+T -40°C to +85°C DS28EC20P+ -40°C to +85°C DS28EC20P+T -40°C to +85°C + Denotes a lead-free package tape and reel TYPICAL OPERATING CIRCUIT (300Ω PUP to 2.2kΩ) PX.Y µ ...
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ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND I/O Sink Current Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, ...
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PARAMETER SYMBOL EEPROM Programming Current I PROG Programming Time t PROG Write/Erase Cycles (Endurance) (Notes 21, N 22) Data Retention t DR (Notes 23, 24, 25) Note 1: Specifications -40°C are guaranteed by design only and not ...
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SUPPLY ELECTRICAL CHARACTERISTICS (T = 0°C to +70° 3.3V ± 5%) A PUP PARAMETER SYMBOL I/O PIN GENERAL DATA 1-Wire Pullup Resistance R Input Capacitance C Input Load Current High-to-Low Switching V Threshold Input Low Voltage V ...
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Note 1: System requirement. Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and current requirements during EEPROM programming. The specified value here applies to systems with only ...
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... The DS28EC20 combines 20Kb of data EEPROM with a fully featured 1-Wire interface in a single chip. The memory is organized as 80 pages of 256 bits each. In addition, the device has one page for control functions such as permanent write protection and EPROM-Emulation mode for individual 2048-bit (8-page) memory blocks. A volatile 256-bit memory page called the scratchpad acts as a buffer when writing data to the EEPROM to ensure data integrity ...
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... CRC returns the shift register to all 0s. Figure 3. 64-Bit Lasered ROM MSB 8-Bit CRC Code MSB LSB MSB iButton is a registered trademark of Maxim Integrated Products, Inc ±5%. The protocol required for these ROM function PUP Available Data Field Commands: Affected: Read ROM 64-bit Reg ...
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... The protection control registers, along with the Memory Block Lock byte, determine whether write protection, EPROM mode, or copy protection is enabled for each of the 10 data memory blocks. A value of 55h sets write protection for the associated memory block. A value of AAh sets EPROM mode. The Memory Block Lock byte, if programmed to either 55h or AAh, sets copy protection for all write-protected data memory blocks ...
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... Figure 5. Memory Map ADDRESS RANGE TYPE 0000h to 00FFh R/(W) 0100h to 01FFh R/(W) 0200h to 02FFh R/(W) 0300h to 03FFh R/(W) 0400h to 04FFh R/(W) 0500h to 05FFh R/(W) 0600h to 06FFh R/(W) 0700h to 07FFh R/(W) 0800h to 08FFh R/(W) 0900h to 09FFh R/(W) 0A00h* to 0A09h* R/(W) 0A0Ah to 0A1Dh ...
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... A valid write to the scratchpad clears the PF bit. Bit 6 has no function; it always reads 0. The highest valued bit of the E/S register, called authorization accepted (AA), is valid only if the PF flag reads and the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag. ...
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... AND of the transmitted data and the data already in memory. The DS28EC20’s memory address range is 0000h to 0A3Fh. If the bus master sends a target address higher than this, the DS28EC20’s internal circuitry sets the four most significant address bits to zero as they are shifted into the internal address register ...
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... If the memory is write-protected, the DS28EC20 copies the data byte from the target address into the scratchpad. Master TX Data Byte If the memory is in EPROM mode, the To Scratchpad Offset DS28EC20 stores the bitwise logical AND of the transmitted byte and the data byte from the targeted address into the scratchpad ...
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... Figure 7-2. Memory Function Flow Chart (continued) From Figure Part DS28EC20 Increments Scratchpad Offset Bus Master RX “1”s To Figure Part AAh N Read Scratch- Pad ? Y Bus Master RX TA1 (T[7:0]), TA2 (T[15:8]) and E/S Byte DS28EC20 sets Scratch- pad Offset = (T[4:0]) Bus Master RX Data Byte ...
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... Figure 7-3. Memory Function Flow Chart (continued) From Figure Part Copy Scratch- Bus Master TX TA1 (T[7:0]), TA2 (T[15:8]) and E/S Byte Auth. Code Bus Master TX Reset ? To Figure Part 55h N Pad ? Y Y Match ? N RX “1”s N Master Y * 1-Wire idle high for t for power ...
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... Figure 7-4. Memory Function Flow Chart (continued) From Figure 7, rd F0h 3 Part Read Memory ? Bus Master TX Decision TA1 (T[7:0]), made by TA2 (T[15:8]) DS28EC20 DS28EC20 sets Memory Address = (T[15:0]) Bus Master RX Data Byte from Memory Address DS28EC20 Increments Address Counter Master TX Reset? ...
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... A pattern of alternating 0s and 1s are transmitted after the data has been copied until the master issues a reset pulse. If the PF flag or BS flag is set or the target memory is copy protected, the copy does not begin and the AA flag is not set. The BS flag ensures that Copy Scratchpad is not executed (blocked) if there was a Read Memory or Extended Read Memory between Write Scratchpad and Copy Scratchpad ...
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... TRANSACTION SEQUENCE The protocol for accessing the DS28EC20 through the 1-Wire port is as follows: Initialization ROM Function Command Memory Function Command Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28EC20 is on the bus and is ready to operate ...
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... To maximize the data throughput in a multidrop environment, the Resume function is available. This function checks the status of the RC bit and set, directly transfers control to the memory functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command ...
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... DS28EC20 TX Bit 1 Master TX Bit 1 DS28EC20 TX Bit 1 Master TX Bit Bit 1 Bit 1 Match? Match? Y DS28EC20 TX Bit 63 Master TX Bit 63 DS28EC20 TX Bit 63 Master TX Bit Bit 63 Bit 63 Match? Match Memory Functions Flow Chart (Figure From Figure F0h CCh N Skip ROM Command From Figure 9, nd Part To Figure Part N ...
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Figure 9-2. ROM Functions Flow Chart (continued Figure 9, 1 Part From Figure Part Command? From Figure Part To Figure Part NOTE: For operation at overdrive speed, the DS28EC20 ...
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... Figure 10 shows the initialization sequence required to begin any communication with the DS28EC20. A reset pulse followed by a presence pulse indicates that the DS28EC20 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for compensate for the edge ...
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Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the V time t is expired. For a write-zero time slot, the voltage on the data line must stay below the V W1LMAX until the ...
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Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V read low time t is expired. During the t RL line low; its internal timing generator determines when this ...
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... With the initial pass through the extended read memory flow, the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the data bytes. Subsequent passes through the extended read memory flow generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the data bytes ...
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... Transfer of as many bytes as needed to reach the end of the scratchpad for a given <data to EOS> target address. <data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory. Transfer of as many data bytes as are needed to reach the end of the page for a given <data to EOP> target address. ...
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... READ MEMORY (CANNOT FAIL) RST PD Select RM TA EXTENDED READ MEMORY (CANNOT FAIL) RST PD Select ERM TA PACKAGE INFORMATION For the latest package outline information www.maxim-ic.com/DallasPackInfo. <Data to EOM> FF Loop <Data to EOP> CRC16\ <32 Bytes> CRC16\ Loop ...
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... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without MAXIM is a registered trademark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation. DESCRIPTION notice at any time. © ...