DS1249W-150 Maxim Integrated Products, DS1249W-150 Datasheet - Page 2

• Manufacturer Part Number: DS1249W-150
• Description: IC NVSRAM 2MBIT 150NS 32DIP
• Manufacturer: Maxim Integrated Products

Specifications of DS1249W-150

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 2M (256K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-DIP Module (600 mil), 32-EDIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

READ MODE
The DS1249 devices execute a read cycle whenever
Enable) and
(A
data output drivers within t
must be measured from the later-occurring signal (
WRITE MODE
The DS1249 executes a write cycle whenever the
inputs are stable. The later-occurring falling edge of
The write cycle is terminated by the earlier rising edge of
valid throughout the write cycle.
before another cycle can be initiated. The
cycles to avoid bus contention. However, if the output drivers are enabled (
will disable the outputs in t
DATA-RETENTION MODE
The DS1249W provides full functional capability for V
2.8V. Data is maintained in the absence of V
static RAMs constantly monitor V
write protects themselves, all inputs become “don’t care,” and all outputs become high impedance. As
V
RAM to retain data. During power-up, when V
circuit connects external V
operation can resume after V
FRESHNESS SEAL
Each DS1249 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When V
enabled for battery backup operation.
CE
CE
CC
0
– A
or t
and
falls below approximately 2.5V, a power-switching circuit connects the lithium energy source to
OE
17
OE
) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
for
access times are also satisfied. If
OE
OE
(Output Enable) are active (low). The unique address specified by the 18 address inputs
rather than t
ODW
ACC
CC
CC
ACC
CC
to the RAM and disconnects the lithium energy source. Normal RAM
from its falling edge.
(Access Time) after the last address input signal is stable, providing that
exceeds 3.0V.
is first applied at a level greater than V
.
WE
CC
. Should the supply voltage decay, the NV SRAMs automatically
must return to the high state for a minimum recovery time (t
OE
CC
OE
control signal should be kept inactive (high) during write
CC
without any additional support circuitry. The nonvolatile
2 of 8
and
rises above approximately 2.5V, the power-switching
CE
CE
WE
WE
CE
or
or
CC
(Write Enable) is inactive (high) and
and
OE
access times are not satisfied, then data access
WE
CE
greater than 3.0 volts and write protects by
) and the limiting parameter is either t
CE
will determine the start of the write cycle.
or
signals are active (low) after address
WE
. All address inputs must be kept
TP
, the lithium energy source is
CE
and
OE
active), then
CE
DS1249W
CO
(Chip
WE
WR
for
)