UPD44646363AF5-E25-FQ1-A Renesas Electronics America, UPD44646363AF5-E25-FQ1-A Datasheet - Page 18

• Manufacturer Part Number: UPD44646363AF5-E25-FQ1-A
• Description: SRAM DDRII 72MBIT 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44646363AF5-E25-FQ1-A

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II+
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read and Write Cycle
Notes 1. -E20 and –E22 are valid for 2.5 Clock Cycles Read Latency products.
18
Clock
Average Clock cycle time (K, K#)
Clock phase jitter (K, K#)
Clock HIGH time (K, K#)
Clock LOW time (K, K#)
Clock HIGH to Clock# HIGH
(K → K#)
Clock# HIGH to Clock HIGH
(K# → K)
DLL/PLL lock time (K)
K static to DLL/PLL reset
Output Times
CQ HIGH to CQ# HIGH
CQ# HIGH to CQ HIGH
(CQ# → CQ)
K, K# HIGH to output valid
K, K# HIGH to output hold
K, K# HIGH to echo clock valid
K, K# HIGH to echo clock hold
CQ, CQ# HIGH to output valid
CQ, CQ# HIGH to output hold
K HIGH to output High-Z
K HIGH to output Low-Z
CQ, CQ# HIGH to QVLD valid
Setup Times
Address valid to K rising edge
Synchronous load input (LD#),
read write input (R, W#) valid to
K rising edge
Data inputs and write data select
inputs (BWx#) valid to
K, K# rising edge
Hold Times
K rising edge to address hold
K rising edge to
synchronous load input (LD#),
read write input (R, W#) hold
K, K# rising edge to data inputs
and write data select inputs
(BWx#) hold
(CQ → CQ#)
2. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) without the DLL/PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle regardless of RL = 2.0 and 2.5 clock cycles products in this operation. The AC/DC characteristics
cannot be guaranteed, however.
(MAX.) indicates a peak-to-peak value.
Parameter
μ
PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A
TCQHCQ#H
TCQ#HCQH
TCQHQVLD
TKC reset
TCQHQV
TCQHQX
TKHCQV
TKHCQX
TKHK#H
TK#HKH
TKC lock
TKHQX1
TKC var
TKHQV
TKHQX
Symbol
TKHKH
TKHQZ
TAVKH
TDVKH
TKHAX
TKHDX
TKHKL
TKLKH
TIVKH
TKHIX
Preliminary Data Sheet M19960EJ1V0DS
– 0.45
– 0.45
– 0.15
– 0.45
– 0.15 0.15 – 0.15 0.15 – 0.20 0.20 – 0.20 0.20 – 0.20 0.20
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
0.85
0.85
0.33
0.33
0.25
0.33
0.33
0.25
(500 MHz)
2.0
0.4
0.4
0.6
0.6
20
-E20
30
Note1
5.25
0.15
0.45
0.45
0.15
0.45
– 0.45
– 0.45
– 0.15
– 0.45
0.95
0.95
0.28
0.28
(450 MHz)
2.2
0.4
0.4
0.7
0.7
0.4
0.4
0.4
0.4
-E22
20
30
Note1
5.25
0.15
0.45
0.45
0.15
0.45
– 0.45
– 0.45
– 0.20
– 0.45
1.06
1.06
0.81
0.81
0.28
0.28
(400 MHz)
2.5
0.4
0.4
0.4
0.4
0.4
0.4
20
30
-E25
5.25
0.20
0.45
0.45
0.20
0.45
– 0.45
– 0.45
– 0.20
– 0.45
1.28
1.28
1.03
1.03
0.28
0.28
(333 MHz)
3.0
0.4
0.4
0.4
0.4
0.4
0.4
20
30
-E30
5.25
0.20
0.45
0.45
0.20
0.45
– 0.45
– 0.45
– 0.20
– 0.45
1.40
1.40
1.15
1.15
0.28
0.28
(300 MHz)
3.3
0.4
0.4
0.4
0.4
0.4
0.4
20
30
-E33
5.25
0.20
0.45
0.45
0.20
0.45
TKHKH
TKHKH
Unit
ns
ns
ns
ns
μ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Note
2
3
4
5
6
6
7
7
8
8
8
8
8
8