UPD44646363AF5-E22-FQ1-A Renesas Electronics America, UPD44646363AF5-E22-FQ1-A Datasheet - Page 7

• Manufacturer Part Number: UPD44646363AF5-E22-FQ1-A
• Description: SRAM DDRII 72MBIT 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44646363AF5-E22-FQ1-A

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II+
• Memory Size: 72M (2M x 36)
• Speed: 450MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Identification
A
DQ0 to DQxx
LD#
R, W#
BWx#
K, K#
CQ, CQ#
ZQ
DLL#
QVLD
ODT
TMS
TDI
TCK
TDO
V
V
V
V
NC
REF
DD
DD
SS
Symbol
Q
Input
Input/Output
Input
Input
Input
Input
Output
Input
Input
Output
Input
Input
Input
Output
–
Supply
Supply
Supply
–
μ
Type
PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K. All transactions operate on a burst of two words (one clock
period of bus activity). These inputs are ignored when device is deselected, i.e., NOP (LD# =
HIGH).
Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K
and K#. Output data is synchronized to the respective K and K#.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and read/write direction. All transactions operate on a burst of 2
data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must
meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered
and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin
Configurations for signal to data relationships.
See Byte Write Operation for relation between BWx# and DQxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K,
and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees
out of phase with K. All synchronous inputs must meet setup and hold times around the clock
rising edges.
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely
and do not stop when DQ tristates. If K and K# are stopped in the single clock mode, CQ and
CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the system
data bus impedance. DQ, CQ, CQ# and QVLD output impedance are set to 0.2 x RQ, where
RQ is a resistor from this bump to ground. The output impedance can be minimized by directly
connect ZQ to V
output impedance is adjusted every 20
and temperature. After replacement for a resistor, the new output impedance is reset by
implementing power-on sequence.
DLL/PLL Disable: When DLL# is LOW, the operation can be performed at a clock frequency
slower than TKHKH (MAX.) without the DLL/PLL circuit being used. The AC/DC characteristics
cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to
V
Q valid Output: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ#.
ODT Control Input: When the ODT control pin is HIGH, the ODT function is turned on at DQxx
and BWx# pins. The ODT resistors are set to 0.6 x RQ, where RQ is a resistor from ZQ pin
bump to ground. When the ODT Control pin is LOW or No Connect, the ODT function is turned
off. The ODT ON/OFF is set at power-on sequence. The ODT can not change the state after
power-on. To enable ODT function, ODT pin must be HIGH and it can be connected to V
through a 10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG
function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to V
not used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to V
HSTL Input Reference Voltage: Nominally V
buffers.
Power Supply: 1.8 V nominal.
Characteristics for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. See Recommended DC
Operating Conditions and DC Characteristics for range.
Power Supply: Ground
No Connect: These signals are not connected internally.
x9 device uses DQ0 to DQ8.
x18 device uses DQ0 to DQ17.
x36 device uses DQ0 to DQ35.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
DD
Q through a 10 kΩ or less resistor.
Preliminary Data Sheet M19960EJ1V0DS
DD
Q. This pin cannot be connected directly to GND or left unconnected. The
See Recommended DC Operating Conditions and DC
μ
s upon power-up to account for drifts in supply voltage
Description
DD
Q/2. Provides a reference voltage for the input
SS
if the JTAG function is
DD
.
DD
Q
7