AT28C64B-15PC Atmel, AT28C64B-15PC Datasheet - Page 2

• Manufacturer Part Number: AT28C64B-15PC
• Description: IC EEPROM 64KBIT 150NS 28DIP
• Manufacturer: Atmel

Specifications of AT28C64B-15PC

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Block Diagram
Absolute Maximum Ratings*
2
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground .................................-0.6 V to +6.25 V
All Output Voltages
with Respect to Ground ...........................-0.6 V to V
Voltage on OE and A9
with Respect to Ground ..................................-0.6 V to +13.5V
AT28C64B
access times to 150 ns with power dissipation of just 220 mW. When the device is dese-
lected, the CMOS standby current is less than 100 µA.
The AT28C64B is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow writ-
ing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64
bytes of data are internally latched, freeing the address and data bus for other opera-
tions. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected by
DATA POLLING of I/O
for a read or write can begin.
Atmel’s AT28C64B has additional features to ensure high quality and manufacturability.
The device utilizes internal error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available to
guard against inadvertent writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.
ADDRESS
INPUTS
CC
GND
VCC
WE
+ 0.6 V
OE
CE
7
. Once the end of a write cycle has been detected, a new access
OE, CE and WE
*NOTICE:
X DECODER
Y DECODER
LOGIC
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
DATA INPUTS/OUTPUTS
INPUT/OUTPUT
IDENTIFICATION
CELL MATRIX
DATA LATCH
I/O0 - I/O7
BUFFERS
Y-GATING
0270I–PEEPR–08/03