AT45DB011-XC Atmel, AT45DB011-XC Datasheet - Page 5

• Manufacturer Part Number: AT45DB011-XC
• Description: IC FLASH 1MBIT 13MHZ 14TSSOP
• Manufacturer: Atmel

Specifications of AT45DB011-XC

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 1M (512 pages x 264 bytes)
• Speed: 13MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT45DB011XC

Block Erase Addressing
MAIN MEMORY PAGE PROGRAM: This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-in Erase operations. Data is first
shifted into the buffer from the SI pin and then programmed
into a specified page in the main memory. An 8-bit opcode
of 82H is followed by the six reserved bits and 18 address
bits. The nine most significant address bits (PA8-PA0)
select the page in the main memory where data is to be
written, and the next nine address bits (BFA8-BFA0) select
the first byte in the buffer to be written. After all address bits
are shifted in, the part will take data from the SI pin and
store it in the data buffer. If the end of the buffer is reached,
the device will wrap around back to the beginning of the
buffer. When there is a low-to-high transition on the CS pin,
the part will first erase the selected page in main memory to
all 1s and then program the data stored in the buffer into
the specified page in the main memory. Both the erase and
the programming of the page are internally self timed and
should take place in a maximum of time t
time, the status register will indicate that the part is busy.
AUTO PAGE REWRITE: This mode is only needed if multi-
ple bytes within a page or multiple pages of data are
modified in a random fashion. This mode is a combination
of two operations: Main Memory Page to Buffer Transfer
and Buffer to Main Memory Page Program with Built-in
Erase. A page of data is first transferred from the main
memory to the data buffer, and then the same data (from
the buffer) is programmed back into its original page of
main memory. An 8-bit opcode of 58H is followed by the six
reserved bits, nine address bits (PA8-PA0) that specify the
page in main memory to be rewritten, and nine additional
don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will first transfer data from the page in main
memory to the buffer and then program the data from the
buffer back into same page of main memory. The operation
PA8
0
0
0
0
1
1
1
1
•
•
•
PA7
0
0
0
0
1
1
1
1
•
•
•
PA6
0
0
0
0
1
1
1
1
•
•
•
PA5
0
0
0
0
1
1
1
1
•
•
•
EP
. During this
PA4
0
0
1
1
0
0
1
1
•
•
•
is internally self-timed and should take place in a maximum
time of t
that the part is busy.
If a sector is programmed or reprogrammed sequentially
page by page, then the programming algorithm shown in
Figure 1 on page 16 is recommended. Otherwise, if multi-
ple bytes in a page or several pages are programmed
randomly in a sector, then the programming algorithm
shown in Figure 2 on page 17 is recommended.
STATUS REGISTER: The status register can be used to
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compare operation, or the
device density. To read the status register, an opcode of
57H must be loaded into the device. After the last bit of the
opcode is shifted in, the eight bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most signifi-
cant bits of the status register will contain device
information, while the remaining three least significant bits
are reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itself (as long as CS remains low and
SCK is being toggled) starting again with bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/Busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, then the device is not busy and is ready
to accept the next command. If bit 7 is a 0, then the device
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to be output on the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
cause the device to be in a busy state: Main Memory Page
to Buffer Transfer, Main Memory Page to Buffer Compare,
PA3
0
1
0
1
0
1
0
1
•
•
•
EP
. During this time, the status register will indicate
PA2
X
X
X
X
X
X
X
X
•
•
•
PA1
X
X
X
X
X
X
X
X
•
•
•
PA0
X
X
X
X
X
X
X
X
•
•
•
Block
60
61
62
63
0
1
2
3
•
•
•
5