AT25256W-10SI Atmel, AT25256W-10SI Datasheet
AT25256W-10SI
Specifications of AT25256W-10SI
Related parts for AT25256W-10SI
AT25256W-10SI Summary of contents
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... Description The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable pro- grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in ...
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Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125°C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Figure 1. Block Diagram AT25128/256 2 ...
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Table 2. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) IN Note: 1. This parameter is characterized and is not 100% tested. ...
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Table 4. AC Characteristics Applicable over recommended operating range from TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter f SCK Clock Frequency SCK t Input Rise Time RI t Input Fall Time FI t ...
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... Output Disable Time DIS t Write Cycle Time WC (1) Endurance 5.0V, 25°C, Page Mode Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. Serial Interface Description 0872O–SEEPR–03/05 = 40° 85°C, T – AI Voltage 4.5 – 5.5 2.7 – 5.5 1.8 – ...
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... X100 RDSR 0000 X101 WRSR 0000 X001 READ 0000 X011 WRITE 0000 X010 AT25128/256 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array 0872O–SEEPR–03/05 ...
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... WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128/256 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write pro- tection levels and corresponding status register control bits are shown in Table 8 ...
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... When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. WRITE SEQUENCE (WRITE): In order to program the AT25128/256, two separate instructions must be executed ...
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Timing Diagrams (for SPI Mode 0 (0, 0)) Figure 3. Synchronous Data Timing CSS V IH SCK HI 0872O–SEEPR–03/05 The AT25128/256 is ...
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Figure 4. WREN Timing Figure 5. WRDI Timing Figure 6. RDSR Timing CS 0 SCK SI INSTRUCTION HIGH IMPEDANCE SO AT25128/256 MSB ...
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Figure 7. WRSR Timing Figure 8. READ Timing Figure 9. WRITE Timing 0872O–SEEPR–03/05 AT25128/256 11 ...
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Figure 10. HOLD Timing CS SCK HOLD SO AT25128/256 0872O–SEEPR–03/05 ...
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AT25128 Ordering Information (2) Ordering Code AT25128-10PI-2.7 AT25128N-10SI-2.7 AT25128W-10SI-2.7 AT25128N1-10SI-2.7 AT25128T1-10TI-2.7 AT25128-10PI-1.8 AT25128N-10SI-1.8 AT25128W-10SI-1.8 AT25128N1-10SI-1.8 AT25128T1-10TI-1.8 AT25128N-10SJ-2.7 AT25128N-10SJ-1.8 AT25128N-10SE-2.7 Notes: 1. This device is not recommended for new designs. Please refer to AT25128A. 2. For 2.7V devices used in ...
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... Ordering Information (2) Ordering Code AT25256-10PI-2.7 AT25256W-10SI-2.7 AT25256-10CI-2.7 AT25256T2-10TI-2.7 AT25256-10PI-1.8 AT25256W-10SI-1.8 AT25256-10CI-1.8 AT25256T2-10TI-1.8 AT25256W-10SJ-2.7 AT25256W-10SJ-1.8 AT25256W-10SE-2.7 Notes: 1. This device is not recommended for new designs. Please refer to AT25256A. 2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables ...
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Packaging Information 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured ...
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JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R ...
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EIAJ SOIC 1 N Top View e D Side View Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs ...
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LAP Marked Pin1 Indentifier E Top View 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 ...
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JEDEC SOIC 3 2 Top View e D Side View End View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2. Dimension D ...
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TSSOP Top View D A Side View Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for additional information. 2. Dimension D does not include mold ...
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TSSOP Top View A Side View Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional information. 2. Dimension D does not include mold Flash, protrusions ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...