AT45DB161-CI Atmel, AT45DB161-CI Datasheet - Page 3

• Manufacturer Part Number: AT45DB161-CI
• Description: IC FLASH 16MBIT 20MHZ 24CBGA
• Manufacturer: Atmel

Specifications of AT45DB161-CI

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (4096 pages x 528 bytes)
• Speed: 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Memory Architecture Diagram
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Table 1 and Table 2. A valid
instruction starts with the falling edge of CS followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address location. While the CS pin is low, toggling
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 4096
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits. In the AT45DB161, the
first two address bits are reserved for larger density
devices (see Notes on page 10), the next 12 address bits
(PA11-PA0) specify the page address, and the next 10
address bits (BA9-BA0) specify the starting byte address
SECTOR ARCHITECTURE
Sector = 135,168 bytes
SECTOR 10
SECTOR 11
SECTOR 12
SECTOR 13
SECTOR 14
SECTOR 15
SECTOR 0
SECTOR 1
SECTOR 2
SECTOR 3
SECTOR 4
SECTOR 5
SECTOR 6
SECTOR 7
SECTOR 8
SECTOR 9
(128K + 4K)
32 Blocks
(256 Pages)
BLOCK ARCHITECTURE
Block = 4224 bytes
BLOCK 509
BLOCK 510
BLOCK 511
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 66
BLOCK 0
BLOCK 1
(4K + 128)
within the page. The 32 don’t care bits which follow the 24
address bits are sent to initialize the read operation. Fol-
lowing the 32 don’t care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS pin must remain low during the loading of the
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same page. A low-to-high transition on the
CS pin will terminate the read operation and tri-state the
SO pin.
BUFFER READ: Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
buffer 2. To perform a buffer read, the eight bits of the
opcode must be followed by 14 don’t care bits, 10 address
bits, and eight don’t care bits. Since the buffer size is 528
bytes, 10 address bits (BFA9-BFA0) are required to specify
the first byte of data to be read from the buffer. The CS pin
must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data.
When the end of a buffer is reached, the device will
continue reading back at the beginning of the buffer. A low-
to-high transition on the CS pin will terminate the read
operation and tri-state the SO pin.
8 Pages
PAGE ARCHITECTURE
Page = 528 bytes
PAGE 4093
PAGE 4094
PAGE 4095
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
(512 + 16)
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