AT49BV001A-55TI Atmel, AT49BV001A-55TI Datasheet - Page 4

• Manufacturer Part Number: AT49BV001A-55TI
• Description: IC FLASH 1MBIT 55NS 32TSOP
• Manufacturer: Atmel

Specifications of AT49BV001A-55TI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.4
4.4.1
4.4.2
4.5
4.6
4
Erasure
Byte Programming
Boot Block Programming Lockout
AT49BV001A(N)(T)
Chip Erase
Sector Erase
Before a byte can be reprogrammed, the main memory blocks or parameter blocks which con-
tains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire
device can be erased at one time by using a 6-byte software code. The software chip erase
code consists of 6-byte load commands to specific address locations with a specific data pattern
(please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase opera-
tion so that no external clocks are required. The maximum time needed to erase the whole chip
is t
erased.
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter
Block 1, Parameter Block 2, Main Memory Block 1 - 2, but not the boot block. If the Boot Block
Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full
chip erase the device will return back to read mode. Any command during chip erase will be
ignored.
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-
byte parameter block sections and the two main memory blocks can be independently erased
and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector
address is latched on the rising WE edge of the sixth cycle and the 30H data input command is
also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the
sixth cycle. The erase operation is internally controlled; it will automatically time to completion.
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the
device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs
last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming
is completed after the specified t
indicate the end of a program cycle.
The device has one designated block that has a programming lockout feature. This feature pre-
vents programming of data in the designated block once the feature has been enabled. The size
of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be activated;
the boot block’s usage as a write protected region is optional to the user. The address range of
the boot block is 00000 to 03FFF for the AT49BV001A(N) while the address range of the boot
block is 1C000 to 1FFFF for the AT49BV001A(N)T.
EC
. If the boot block lockout feature has been enabled, the data in the boot sector will not be
BP
cycle time. The DATA polling feature may also be used to
“Command Definition Table” on page
3364D–FLASH–3/05
6). The