AT49LH00B4-33JC Atmel, AT49LH00B4-33JC Datasheet - Page 11

• Manufacturer Part Number: AT49LH00B4-33JC
• Description: IC FLASH 4MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH00B4-33JC

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 7-3.
Note:
7.5
3379C–FLASH–3/05
Clock Cycle
13 - 14
3 - 9
10
11
12
15
16
17
18
19
1
2
1. Field contents are valid on the rising edge of the present clock cycle.
FWH Write Cycle
FWH Read Cycle
Field Name
WSYNC
MADDR
RSYNC
START
MSIZE
IDSEL
TAR0
TAR1
DATA
DATA
TAR0
TAR1
FWH write cycles are used to send commands to the device and to program data into the mem-
ory array.
Valid FWH write cycles begin with a START field of 1110b being sent to the device. Following
the IDSEL, MADDR, and MSIZE fields, the master sends one byte of data to the FWH device
during the next two clock cycles. The data is sent one nibble at a time with the low nibble being
output first followed by the high nibble. After the data has been sent, the master will send a
2-clock TAR field to the FWH device to indicate that it is turning control of the LPC bus back over
to the FWH. After the second clock of the TAR phase, the FWH device assumes control of the
bus and drives a “ready” SYNC field to verify that it has received the data. The FWH device will
then send a 2-clock TAR field to the master to indicate that it is turning control of the bus back
over to the master.
0000b to 1111b
FWH/LAD[3:0]
0000b (ready)
Field Value
1111b (float)
1111b (float)
0101b (wait)
(indicates
1 byte)
1101b
0000b
1111b
1111b
YYYY
YYYY
YYYY
(1)
Float then OUT
FWH/LAD[3:0]
OUT then float
Float then IN
IN then float
Direction
OUT
OUT
OUT
OUT
IN
IN
IN
IN
Comments
FWH4/LFRAME must be active (low) for the device to
respond. Only the last START field (before FWH4/LFRAME
transitioning high) should be recognized. The START field
contents indicate a FWH memory read cycle.
Indicates which FWH memory device should respond. If the
IDSEL field matches the strapping values on ID[3:0], then that
particular device will respond to subsequent commands.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address. Addresses
are transferred with the most significant nibble first.
The MSIZE field indicates how many bytes will be transferred.
The device only supports single-byte operations, so MSIZE
must be 0000b.
In this clock cycle, the master has driven the bus to all 1s and
then floats the bus prior to the next clock cycle. This is the first
part of the bus “turn-around cycle”.
The device takes control of the bus during this clock cycle.
The device outputs the value 0101b, a “wait” SYNC, for two
clock cycles. This value indicates to the master that data is not
yet available from the device. This number of wait-syncs is a
function of the device’s memory access time.
During this clock cycle, the device will generate a “ready”
SYNC indicating that the least significant nibble of the data
byte will be available during the next clock cycle.
YYYY is the least significant nibble of the data byte.
YYYY is the most significant nibble of the data byte.
The FWH memory device drives the bus to 1111b to indicate a
turn-around cycle.
The FWH memory device floats its outputs, and the master
regains control of the bus during this clock cycle.
AT49LH00B4
11