AT45DB161D-SU Atmel, AT45DB161D-SU Datasheet - Page 4

• Manufacturer Part Number: AT45DB161D-SU
• Description: IC FLASH 16MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB161D-SU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (4096 pages x 528 bytes)
• Speed: 66MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Architecture: Sectored
• Interface Type: SPI
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 128 KB x 16
• Current, Input, Leakage: 1 μA
• Current, Operating: 11 mA (Read), 12 mA (Program/Erase)
• Current, Output, Leakage: 1
• Data Retention: 20 yrs.
• Density: 16M
• Package Type: EIAJ SOIC
• Temperature, Operating: -40 to +85 °C
• Time, Access: 6 ns
• Time, Address Hold: 5
• Time, Address Setup: 5
• Time, Fall: 6.8 ns
• Time, Rise: 6.8 ns
• Voltage, Input, High: 1.89 to 2.52 V
• Voltage, Input, Low: 0.81 to 1.08 V
• Voltage, Output, High: 2.5 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.7 to 3.6 V
• Memory Configuration: 4096 Pages X 528 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.5V To 3.6V, 2.7V To 3.6V
• Rohs Compliant: Yes
• Access Time (max): 6ns
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Block Diagram
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB161D is divided into three levels of granularity comprising of
sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the
number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase
operations can be performed at the chip, sector, block or page level.
Figure 4-1.
4
SECTOR ARCHITECTURE
RDY/BUSY
AT45DB161D
SECTOR 14 = 256 Pages
SECTOR 15 = 256 Pages
SECTOR 1 = 256 Pages
SECTOR 2 = 256 Pages
SECTOR 0b = 248 Pages
SECTOR 0a = 8 Pages
131,072/135,168 bytes
131,072/135,168
131,072/135,168 bytes
131,072/135,168 bytes
126,976/130,944 bytes
4,096/4,224 bytes
RESET
Memory Architecture Diagram
GND
VCC
SCK
WP
CS
bytes
PAGE (512/528 BYTES)
BUFFER 1 (512/528 BYTES)
SECTOR 0
SI
BLOCK ARCHITECTURE
Block = 4,096/4,224 bytes
FLASH MEMORY ARRAY
BLOCK 510
BLOCK 511
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 0
BLOCK 1
BLOCK 2
I/O INTERFACE
8 Pages
BUFFER 2 (512/528 BYTES)
SO
PAGE ARCHITECTURE
Page = 512/528 bytes
PAGE 4,094
PAGE 4,095
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
3500I–DFLASH–8/07